公开(公告)号：US20050266711A1

公开(公告)日：2005-12-01

申请号：US10711653

申请日：2004-09-29

申请人： Ryan Petersen ,  Eric Nelson

发明人： Ryan Petersen ,  Eric Nelson

IPC分类号： G06F1/26 ,  H01R13/02

CPC分类号： G06F1/26 ,  G11C5/04 ,  G11C5/147

摘要： A method and apparatus for providing power to a memory array of a computer's memory subsystem, and more particularly power at a level greater than that available through the computer motherboard so as to boost memory performance and operational stability. The apparatus includes a supply device for supplying an input voltage to the memory subsystem at a level that is higher than the power level provided to the memory subsystem by the motherboard. The method entails electrically connecting the supply device to the memory subsystem, and then electrically connecting a power source to the device to deliver the input voltage to the memory subsystem. The additional input voltage supplied to the memory subsystem causes memory chips on memory modules of the memory subsystem to run at higher frequencies, such that the various internal operations of the memory, such as reading and writing, occur more quickly.

摘要翻译： 一种用于向计算机的存储器子系统的存储器阵列提供电力的方法和装置，并且更具体地，其功率大于通过计算机主板可用的电平，从而提高存储器性能和操作稳定性。 该装置包括供给装置，用于以高于由主板提供给存储器子系统的功率电平的高度向存储器子系统提供输入电压。 该方法需要将供应装置电连接到存储器子系统，然后将电源电连接到装置以将输入电压传送到存储器子系统。 提供给存储器子系统的附加输入电压使得存储器子系统的存储器模块上的存储器芯片以更高的频率运行，使得诸如读取和写入的存储器的各种内部操作更快地发生。

公开(公告)号：US20060056214A1

公开(公告)日：2006-03-16

申请号：US11161977

申请日：2005-08-24

申请人： Ryan Petersen ,  Eric Nelson

发明人： Ryan Petersen ,  Eric Nelson

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  G11C7/22 ,  G11C7/222

摘要： A memory module capable of exhibiting reduced input clock skew. More particularly, an unbuffered memory module that comprises a substrate, multiple memory components mounted to the substrate, and input/output and address and command bus connectors that transmit digital information to and from the memory components further includes a phase lock loop (PLL) circuit that electrically interconnects a clock-in connector to the memory components for generating and transmitting a module clock signal to the memory components without routing any information to the memory components through a register. In this manner, the PLL operates to provide the memory module with an onboard clock generator that synchronizes the memory components of the module.

摘要翻译： 能够显示减少的输入时钟偏移的存储器模块。 更具体地，包括衬底，安装到衬底的多个存储器组件以及向存储器组件传送数字信息的输入/输出以及地址和命令总线连接器的无缓冲存储器模块还包括锁相环（PLL）电路 将时钟输入连接器电连接到存储器组件，用于生成模块时钟信号并将其发送到存储器组件，而不通过寄存器将任何信息路由到存储器组件。 以这种方式，PLL操作以向存储器模块提供同步模块的存储器组件的板载时钟发生器。

公开(公告)号：US20070159789A1

公开(公告)日：2007-07-12

申请号：US11621396

申请日：2007-01-09

申请人： Franz Schuette ,  Ryan Petersen ,  Eric Nelson ,  Bhulinder Sethi

发明人： Franz Schuette ,  Ryan Petersen ,  Eric Nelson ,  Bhulinder Sethi

IPC分类号： G06F1/20

CPC分类号： G06F1/206

摘要： A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body.

摘要翻译： 一种用于通过促进存储器模块的自然对流冷却来对计算机存储器模块进行热管理的散热器和方法。 散热器包括围绕适于安装到计算机的存储器模块的平面主体的框架，以及通过多个均匀分布的穿孔限定在平面主体中的格栅。 穿孔延伸穿过平面体，以允许平面体下面的内部空间与平面体上方的外部空间之间的自然约定。

公开(公告)号：US20060056215A1

公开(公告)日：2006-03-16

申请号：US11162029

申请日：2005-08-25

申请人： Ryan Petersen ,  Franz Schuette

发明人： Ryan Petersen ,  Franz Schuette

IPC分类号： G11C5/02

CPC分类号： G11C7/1078 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H05K1/0246 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

摘要： A memory module adapted for installation in an open memory socket on a mainboard of a computer. The memory module includes a substrate with an edge connector comprising pins along an edge of the substrate, and at least one memory package mounted to the substrate and containing a memory die electrically connected to input/output leads located along the perimeter of the memory package and through which data signals are transmitted to and from the memory die. Data signal lines electrically connect a plurality of the input/output leads of the memory package to a plurality of the pins of the edge connector. Termination resistors individually electrically connect each of the data signal lines to ground, a supply voltage, or a reference voltage of the memory package so as to reduce noise and signal reflections through the data signal lines.

摘要翻译： 一种适于安装在计算机主板上的开放存储器插槽中的存储器模块。 存储器模块包括具有边缘连接器的基板，该边缘连接器包括沿着基板的边缘的引脚，以及安装到基板的至少一个存储器封装，并且包含电连接到沿着存储器封装周边的输入/输出引线的存储器管芯， 数据信号通过该数据信号发送到存储器管芯和从存储器管芯传送。 数据信号线将存储器封装的多个输入/输出引线电连接到边缘连接器的多个引脚。 端接电阻器将每个数据信号线电连接到存储器封装的地，电源电压或参考电压，以便减少通过数据信号线的噪声和信号反射。

公开(公告)号：US20050226076A1

公开(公告)日：2005-10-13

申请号：US10907420

申请日：2005-03-31

申请人： Ryan Petersen

发明人： Ryan Petersen

IPC分类号： G06F1/26 ,  G11C5/00 ,  G11C5/14 ,  H05K1/02 ,  H05K1/14

CPC分类号： G06F1/26 ,  G11C5/147 ,  H05K1/0231 ,  H05K1/141 ,  H05K2201/044

摘要： An apparatus for buffering power transients in a supply power for expansion cards inserted into expansion slots on a computer motherboard. The apparatus comprises a printed circuit board, a connector on the printed circuit board, and at least one capacitor on the printed circuit board. The connector is configured to fit into one of the expansion slots on the motherboard, and comprises at least one power pin and at least one ground pin. The at least one capacitor is connected to the power and ground pins of the connector and has sufficient capacitance to buffer power transients within the supply power to the expansion slots.

摘要翻译： 一种用于缓冲插入到计算机主板上的扩展槽中的扩展卡的供电电源瞬态的装置。 该装置包括印刷电路板，印刷电路板上的连接器和印刷电路板上的至少一个电容器。 连接器被配置成装配到主板上的一个扩展槽中，并且包括至少一个电源引脚和至少一个接地引脚。 至少一个电容器连接到连接器的电源和接地引脚，并且具有足够的电容以缓冲对扩展槽的供电的功率瞬变。

公开(公告)号：US08151030B2

公开(公告)日：2012-04-03

申请号：US11138768

申请日：2005-05-25

申请人： Ryan Petersen ,  Franz Michael Schuette

发明人： Ryan Petersen ,  Franz Michael Schuette

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C7/22 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth. These optimizations in the SPD allow for much better bandwidth in real world applications.

摘要翻译： 本发明提供了一种在DDR SDRAM模块中增加DDR存储器带宽的方法。 DDR存储器具有称为可变早期读取命令的固有功能，其中读取命令在正在进行的数据突发终止之前发出一个CAS延迟通过使用可变早期读取命令，CAS延迟的影响在效果方面被最小化 带宽。 通过本发明实现的增强带宽技术优化了用于最佳带宽的剩余的两个接入延迟（tRP和tRCD）。 SPD中的这些优化可以在现实世界的应用中实现更好的带宽。

公开(公告)号：US07876564B2

公开(公告)日：2011-01-25

申请号：US12127133

申请日：2008-05-27

申请人： Mohasit Monh ,  Ryan Petersen

发明人： Mohasit Monh ,  Ryan Petersen

IPC分类号： H05K7/20 ,  H01L23/34 ,  F28F7/00

CPC分类号： H01L23/427 ,  F28D15/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for cooling chips on a computer memory module. The apparatus includes a primary and secondary heat spreaders, at least a first heatpipe coupled to the primary heat spreader and having a remote portion spaced apart from the primary heat spreader and thermally contacting the secondary heat spreader, and a coolant within the first heatpipe and the primary heat spreader so as to absorb heat from the primary heat spreader and conduct the heat to the secondary heat spreader. The primary heat spreader has at least two panels configured to engage the memory module therebetween, with facing contact surfaces of the panels adapted for thermal contact with the module chips. The secondary heat spreader is configured to increase surface dissipation of heat from the first heatpipe into the environment. The coolant has a boiling point at or below a maximum preselected operating temperature of the module chips.

摘要翻译： 一种用于在计算机存储器模块上冷却芯片的方法和装置。 该装置包括主和二次散热器，至少第一热管与第一散热器相连，并且具有与初级散热器间隔开并与第二散热器热接触的远端部分，以及第一热管内的冷却剂和 初级散热器，以便从主散热器吸收热量并将热量传导到二次散热器。 主散热器具有至少两个配置成与其间的存储器模块接合的面板，面板的面对的接触表面适于与模块芯片热接触。 二次散热器被配置为增加热量从第一热管到环境中的表面散热。 冷却剂具有等于或低于模块芯片的最大预选工作温度的沸点。

公开(公告)号：US20080049960A1

公开(公告)日：2008-02-28

申请号：US11845896

申请日：2007-08-28

申请人： Ryan Petersen ,  Franz Schuette

发明人： Ryan Petersen ,  Franz Schuette

IPC分类号： H04R25/00

CPC分类号： H04R1/083 ,  H04R1/028

摘要： A gaming headset adapted for precise delivery of chemical substances capable of olfactory stimulation, such as odorants, fragrances, pheromones, etc. The headset includes at least one earpiece containing a speaker, a feature for securing the earpiece to the person's head while positioning the speaker over one of the person's ears when the headset is worn, an armature disposed relative to the earpiece so as to extend toward the person's mouth, a microphone located on the armature so as to be located in front of the person's mouth, and a feature supported by and extending along the armature for delivering at least one chemical substance to the person's nostril's when the headset is worn.

摘要翻译： 适用于精确输送能够嗅觉刺激的化学物质的游戏耳机，例如气味剂，香料，信息素等。头戴式耳机包括至少一个包含扬声器的耳塞，用于将耳机固定到人的头部并将扬声器定位的特征 在耳机佩戴时超过人的耳朵之一，相对于耳机设置的电枢朝向人的嘴部延伸，位于电枢上的麦克风位于人的嘴前面，并且支撑的特征 沿着衔铁延伸并在耳机佩戴时将至少一种化学物质递送到人的鼻孔。

公开(公告)号：US20080291630A1

公开(公告)日：2008-11-27

申请号：US12127133

申请日：2008-05-27

申请人： Mohasit Monh ,  Ryan Petersen

发明人： Mohasit Monh ,  Ryan Petersen

IPC分类号： H05K7/20

CPC分类号： H01L23/427 ,  F28D15/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for cooling chips on a computer memory module. The apparatus includes a primary and secondary heat spreaders, at least a first heatpipe coupled to the primary heat spreader and having a remote portion spaced apart from the primary heat spreader and thermally contacting the secondary heat spreader, and a coolant within the first heatpipe and the primary heat spreader so as to absorb heat from the primary heat spreader and conduct the heat to the secondary heat spreader. The primary heat spreader has at least two panels configured to engage the memory module therebetween, with facing contact surfaces of the panels adapted for thermal contact with the module chips. The secondary heat spreader is configured to increase surface dissipation of heat from the first heatpipe into the environment. The coolant has a boiling point at or below a maximum preselected operating temperature of the module chips.

摘要翻译： 一种用于在计算机存储器模块上冷却芯片的方法和装置。 该装置包括主和二次散热器，至少第一热管与第一散热器相连，并且具有与初级散热器间隔开并与第二散热器热接触的远端部分，以及第一热管内的冷却剂和 初级散热器，以便从主散热器吸收热量并将热量传导到二次散热器。 主散热器具有至少两个配置成与其间的存储器模块接合的面板，面板的面对的接触表面适于与模块芯片热接触。 二次散热器被配置为增加热量从第一热管到环境中的表面散热。 冷却剂具有等于或低于模块芯片的最大预选工作温度的沸点。

公开(公告)号：US20070005902A1

公开(公告)日：2007-01-04

申请号：US11164838

申请日：2005-12-07

申请人： Ryan Petersen ,  Franz Schuette

发明人： Ryan Petersen ,  Franz Schuette

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0893 ,  G06F2212/3042

摘要： A memory module having at least one random access memory device and a memory bus on a substrate. The memory module further comprises an SRAM cache interfaced with the random access memory device through an ASIC associated with the SRAM cache and operable as a prefetch controller for the SRAM cache. The ASIC and SRAM cache cooperate to enable data to be prefetched and cached during idle cycles of the memory device, thereby increasing the overall operating speed of the memory circuit by minimizing latencies should the prefetched data be requested. The ASIC can be programmed to prefetch not only data from the originally accessed row during a read operation, but also to speculatively prefetch data from logically coherent rows in order to anticipate and counteract a page miss and the associated latencies based on the locality of data.

摘要翻译： 一种在基板上具有至少一个随机存取存储器件和存储器总线的存储器模块。 存储器模块还包括通过与SRAM高速缓存相关联的ASIC与随机存取存储器设备连接的SRAM高速缓存，并且可用作用于SRAM缓存的预取控制器。 ASIC和SRAM缓存协作以使数据在存储器件的空闲周期期间被预取和高速缓存，从而通过在请求预取数据的情况下最小化延迟来增加存储器电路的总体操作速度。 ASIC可以被编程为在读取操作期间不仅从原始访问的行预取数据，而且还可以从逻辑上相干行推测性地预取数据，以便基于数据的位置来预测和抵消页面未命中和相关联的延迟。