公开(公告)号：US5396185A

公开(公告)日：1995-03-07

申请号：US100252

申请日：1993-08-02

申请人： Ryoji Honma ,  Soichi Kawasaki ,  Hidetaka Tone ,  Hiroyuki Ohira ,  Kouichi Watanabe

发明人： Ryoji Honma ,  Soichi Kawasaki ,  Hidetaka Tone ,  Hiroyuki Ohira ,  Kouichi Watanabe

IPC分类号： H01L21/66 ,  G01R1/04 ,  H01L21/48 ,  G01R31/28

CPC分类号： G01R1/04

摘要： A plurality of semiconductor integrated circuit devices are mounted on a film carrier. First electrical connecting sections and first electrical wiring sections for electrically connecting the first electrical connecting sections to the semiconductor integrated circuit devices are provided on the film carrier. Second and third electrical connecting sections and second electrical wiring sections are provided on a film-like probe for electrical characteristic test. The second electrical connecting sections are provided in position corresponding to the first electrical connecting sections of the film carrier. The third electrical connecting sections are used to supply electrical signals to the exterior or derive an electrical signal to the exterior and check the electrical signal. The second electrical wiring sections electrically connects the second and third electrical connecting sections to each other. When the test is effected, the film-like probe and the film carrier are superposed on each other so as to set the second electrical connecting sections of the film-like probe into contact with the first electrical connecting sections of the film carrier. The electrical characteristic test of the semiconductor integrated circuit devices are effected by supplying electrical signals necessary for the electrical characteristic test of the semiconductor integrated circuit devices from the exterior via the third electrical connecting sections or deriving the electrical signals to the exterior and checking the electrical signals.

摘要翻译： 多个半导体集成电路器件安装在薄膜载体上。 第一电连接部分和用于将第一电连接部分电连接到半导体集成电路器件的第一电连接部分设置在胶片载体上。 第二和第三电连接部分和第二电连接部分设置在用于电特性测试的膜状探针上。 第二电连接部设置在与胶片承载体的第一电连接部对应的位置。 第三电连接部分用于向外部提供电信号，或者将电信号导出到外部并检查电信号。 第二电气配线部将第二和第三电连接部彼此电连接。 当进行测试时，将膜状探针和薄膜载体彼此叠置，以将薄膜状探针的第二电连接部分与薄膜载体的第一电连接部分接触。 半导体集成电路器件的电特性测试通过经由第三电连接部分从外部提供半导体集成电路器件的电特性测试所需的电信号或者将电信号导出到外部并检查电信号来实现 。

公开(公告)号：US5237268A

公开(公告)日：1993-08-17

申请号：US742426

申请日：1991-08-07

申请人： Ryoji Honma ,  Soichi Kawasaki ,  Hidetaka Tone ,  Hiroyuki Ohira ,  Kouichi Watanabe

发明人： Ryoji Honma ,  Soichi Kawasaki ,  Hidetaka Tone ,  Hiroyuki Ohira ,  Kouichi Watanabe

IPC分类号： H01L21/66 ,  G01R1/04 ,  H01L21/48

CPC分类号： G01R1/04

摘要： A plurality of semiconductor integrated circuit devices are mounted on a film carrier. First electrical connecting sections and first electrical wiring sections for electrically connecting the first electrical connecting sections to the semiconductor integrated circuit devices are provided on the film carrier. Second and third electrical connecting sections and second electrical wiring sections are provided on a film-like probe for electrical characteristic test. The second electrical connecting sections are provided in position corresponding to the first electrical connecting sections of the film carrier. The third electrical connecting sections are used to supply electrical signals to the exterior or derive an electrical signal to the exterior and check the electrical signal. The second electrical wiring sections connects the second and third electrical connecting sections to each other. The film-like probe and the film carrier are superposed on each other so as to set the second electrical connecting sections of the filmlike probe into contact with the first electrical connecting sections of the film carrier.

摘要翻译： 多个半导体集成电路器件安装在薄膜载体上。 第一电连接部分和用于将第一电连接部分电连接到半导体集成电路器件的第一电连接部分设置在胶片载体上。 第二和第三电连接部分和第二电连接部分设置在用于电特性测试的膜状探针上。 第二电连接部设置在与胶片承载体的第一电连接部对应的位置。 第三电连接部分用于向外部提供电信号，或者将电信号导出到外部并检查电信号。 第二电连接部将第二和第三电连接部彼此连接。 膜状探针和薄膜载体彼此重合，以使膜状探针的第二电连接部分与薄膜载体的第一电连接部分接触。

公开(公告)号：US5687180A

公开(公告)日：1997-11-11

申请号：US454702

申请日：1995-05-31

申请人： Soichi Kawasaki

发明人： Soichi Kawasaki

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3173

CPC分类号： G01R31/31715 ,  G01R31/318572

摘要： Output signals of input buffers connected to the external input terminals of the semiconductor circuit are stored in respective memories. The memories are connected in series. Data of the memories are serially output from an external output terminal of the semiconductor circuit. In the above-mentioned operations, a pulse for storing the output signals of the input buffers into the memories, for selecting one of an output signal of the internal circuit and the data stored in the memories, and outputting the selected one from the external output terminal, is supplied via another external input terminal for a test. A pulse for connecting the memories in series is also supplied via a further external input terminal. The output signals of the input buffers can be output from the semiconductor circuit, without any operation of the internal circuit.

摘要翻译： 连接到半导体电路的外部输入端子的输入缓冲器的输出信号存储在相应的存储器中。 这些记忆是串联的。 存储器的数据从半导体电路的外部输出端子串行输出。 在上述操作中，用于将输入缓冲器的输出信号存储到存储器中的脉冲，用于选择内部电路的输出信号和存储在存储器中的数据中的一个，并从外部输出中输出所选择的一个 端子，通过另一个外部输入端子进行测试。 用于连接存储器串联的脉冲也通过另外的外部输入端子提供。 输入缓冲器的输出信号可以从半导体电路输出，而不需要内部电路的任何操作。

公开(公告)号：US5557766A

公开(公告)日：1996-09-17

申请号：US964142

申请日：1992-10-21

申请人： Nobuhiro Takiguchi ,  Soichi Kawasaki ,  Yasuo Yamada ,  Akira Kanuma

发明人： Nobuhiro Takiguchi ,  Soichi Kawasaki ,  Yasuo Yamada ,  Akira Kanuma

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/40

CPC分类号： G06F9/462

摘要： A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers. The bank specifying registers include a current bank pointer (CBP) or register for indicating a position of a bank presently in use, and a previous bank pointer (PBP) or register for indicating a bank position of data to be returned to the data memories after completing an interrupt routine. The processor may also include a program counter (PC) for indicating an address of a next instruction to be executed by the processor, a processor status word (PSW) for indicating a status of the processor, and a user stack pointer (USP) for indicating an address of a bank storing values of the program counter.

摘要翻译： 处理器包括银行结构的存储器并且能够处理多个中断。 该处理器包括一个中央处理单元（CPU），包括用作通用寄存器的多个数据存储器，以及多个存储体指定寄存器，用于指定地址以保存和恢复数据，而不涉及连接外部系统总线的外部系统总线 CPU和诸如内置只读存储器（ROM）的程序存储器，用于存储用户程序。 处理器还包括银行结构化存储器，其通过专用数据总线连接到CPU，用于使用存储体指定寄存器保存存储在数据存储器中的数据，并使用存储体结构存储器将存储在存储体结构存储器中的数据返回给数据存储器 银行指定寄存器。 存储体指定寄存器包括用于指示当前正在使用的存储体的位置的当前存储体指针（CBP）或寄存器，以及用于指示要返回数据存储器的数据的存储单元位置的先前存储体指针（PBP）或寄存器， 完成一个中断程序。 处理器还可以包括用于指示要由处理器执行的下一条指令的地址的程序计数器（PC），用于指示处理器的状态的处理器状态字（PSW）以及用于指示处理器的状态的用户堆栈指针（USP） 指示存储程序计数器的值的存储体的地址。

公开(公告)号：US5150389A

公开(公告)日：1992-09-22

申请号：US645403

申请日：1991-01-24

申请人： Soichi Kawasaki

发明人： Soichi Kawasaki

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G11C19/00

CPC分类号： G11C19/00

摘要： The input nodes and output nodes of a plurality of storing circuits for storing plural-bit data are connected to one another to constitute a shift register. Each of the plurality of storing circuits includes a selection circuit for selecting 1-bit data from the plural-bit data according to a selection signal, a first latch circuit for latching the 1-bit data selected by the selection circuit in synchronism with a first clock signal, and a number of second latch circuits, which number corresponds to the number of bits of input data, for latching an output of the first latch circuit in synchronism with a plurality of second clock signals having phases different from that of the first clock signal. Data sequentially selected by the selection circuit is latched into the first latch circuit and then sequentially latched into the second latch circuit in a time-sharing fashion.

摘要翻译： 用于存储多位数据的多个存储电路的输入节点和输出节点彼此连接以构成移位寄存器。 多个存储电路中的每一个包括用于根据选择信号从多位数据中选择1位数据的选择电路，用于锁存由选择电路选择的1位数据与第一 时钟信号和多个第二锁存电路，其数量对应于输入数据的位数，用于与第一时钟的相位不同的多个第二时钟信号同步地锁存第一锁存电路的输出 信号。 由选择电路顺序选择的数据被锁存在第一锁存电路中，然后以分时方式顺序地锁存到第二锁存电路中。

公开(公告)号：US5561818A

公开(公告)日：1996-10-01

申请号：US31200

申请日：1993-03-12

申请人： Soichi Kawasaki

发明人： Soichi Kawasaki

IPC分类号： G06F9/34 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48 ,  G06F12/06 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F9/462

摘要： A microprocessor having a register file inside is so combined with an external memory through a dedicated high-speed bus that the memory operates as a bank for said register file. This microprocessor further has means for controlling a data transfer with said memory or peripheral devices. When an address information to access said memory is input to this microprocessor in order to control a data transfer between said memory and a peripheral device, said control means finds if the accessed area in said memory is now in use as a bank for said register file, or not. When it is in use, said control means controls a data transfer between said peripheral device and said register file, instead of controlling the data transfer between said memory and said peripheral device. So, said peripheral device can always access the newest information in said memory.

摘要翻译： 具有寄存器文件内部的微处理器通过专用高速总线与外部存储器组合，存储器作为用于所述寄存器文件的存储器操作。 该微处理器还具有用于利用所述存储器或外围设备控制数据传输的装置。 当访问所述存储器的地址信息被输入到该微处理器以便控制所述存储器和外围设备之间的数据传输时，所述控制装置发现所述存储器中的被访问区域现在是否被用作用于所述寄存器文件的存储体 ， 或不。 在使用时，所述控制装置控制所述外围设备与所述寄存器文件之间的数据传送，而不是控制所述存储器和所述外围设备之间的数据传输。 因此，所述外围设备可以随时访问所述存储器中的最新信息。

公开(公告)号：US5471484A

公开(公告)日：1995-11-28

申请号：US854897

申请日：1992-03-20

申请人： Soichi Kawasaki

发明人： Soichi Kawasaki

IPC分类号： G01R31/28 ,  G01R31/3193 ,  H03K19/00 ,  G06F11/00

CPC分类号： G01R31/31937

摘要： A logical circuit is tested by comparing at least one arbitrary bit of a logical signal among logical signals outputted from the logical circuit with an expected value corresponding to the correct level of the logical signal, and comparing a bit position at which the level of the logical signal changes with an expected change point indicating a bit position at which the level of the correct logical signal changes. Such a test can be performed using a tester having a first comparator for comparing a logical signal outputted from a logical circuit to be tested with an expected value corresponding to the correct level of the logical signal, during at least one arbitrary unit test cycle, a change point detecting unit for detecting a time of level change of the logical signal and outputting change point information, by comparing the logical signal delayed by the unit test cycle with the logical signal not delayed, an expected change point generator for generating an expected change point signal indicating a bit position at which the level of the correct logical signal changes, and a second comparator for comparing the change point information with the expected change point signal, wherein the logical circuit is tested using the comparison results of the first and second comparators.

摘要翻译： 通过将从逻辑电路输出的逻辑信号中的逻辑信号的至少一个任意位与对应于逻辑信号的正确电平的期望值进行比较来测试逻辑电路，以及比较逻辑 信号随预期的变化点变化，表示正确的逻辑信号的电平改变的位位置。 这样的测试可以使用具有第一比较器的测试器，该测试器在至少一个任意单位测试周期内比较从待测试的逻辑电路输出的逻辑信号与对应于逻辑信号的正确电平的期望值 变化点检测单元，用于通过将延迟单元测试周期的逻辑信号与未延迟的逻辑信号进行比较来检测逻辑信号的电平变化时间并输出变化点信息，用于产生预期变化点的预期变化点发生器 指示正确逻辑信号的电平改变的位位置的信号，以及用于将改变点信息与预期变化点信号进行比较的第二比较器，其中使用第一和第二比较器的比较结果测试逻辑电路。

公开(公告)号：US5175447A

公开(公告)日：1992-12-29

申请号：US687616

申请日：1991-04-19

申请人： Soichi Kawasaki ,  Takashi Yoshimori ,  Keiji Matsumoto

发明人： Soichi Kawasaki ,  Takashi Yoshimori ,  Keiji Matsumoto

IPC分类号： G01R31/28 ,  H03K3/037

CPC分类号： H03K3/0375

摘要： A multifunctional scan flip-flop having a normal function and a scan function, including: a first latch used for a normal function for latching input data applied to a data input terminal during a normal function operation, the latch operation being carried out synchronous with a clock applied to a clock input terminal; a second latch used for a scan function for holding scan data applied to a scan data input terminal during a scan function operation; and a delay circuit for delaying one of the input data and the clock relative to the other, the delay operation being carried out in accordance with the H/L level of the scan data held by the second latch.

摘要翻译： 一种具有正常功能和扫描功能的多功能扫描触发器，包括：用于正常功能的第一锁存器，用于锁定在正常功能操作期间施加到数据输入端子的输入数据，所述锁存操作与 时钟施加到时钟输入端子; 用于在扫描功能操作期间用于保持施加到扫描数据输入端的扫描数据的扫描功能的第二锁存器; 以及延迟电路，用于相对于另一个延迟输入数据和时钟中的一个，所述延迟操作是根据由第二锁存器保持的扫描数据的H / L电平执行的。