公开(公告)号：US20180090273A1

公开(公告)日：2018-03-29

申请号：US15481157

申请日：2017-04-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Sun HWANG ,  Myung Sam KANG ,  Dong Keun LEE

IPC: H01G4/248 ,  H01G4/30 ,  H01G4/012

CPC classification number: H01G4/248 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/1236 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  H01G4/308 ,  Y02E60/13

Abstract: A multilayer capacitor includes a body including dielectric layers and first and second internal electrodes alternately disposed with dielectric layers interposed therebetween. First and second external electrodes are on the body and connected to the first and second internal electrodes, respectively. The first and second internal electrodes are plating layers. A manufacturing method of a multilayer capacitor includes preparing a plurality of laminated sheets including internal electrodes, dummy electrodes, and dielectric layers. The plurality of laminated sheets, and covers on and below the laminated sheets, are simultaneously stacked and then cured to prepare a cured product. The cured product is then diced depending on the size of the capacitor to prepare a body where the internal electrodes and the dummy electrodes are partially exposed. External electrodes are formed on external surfaces of the body using the dummy electrodes as seeds in a plating method.

公开(公告)号：US20240215157A1

公开(公告)日：2024-06-27

申请号：US18382202

申请日：2023-10-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Ran PARK ,  Hyun Woo KWON ,  Tae Hong MIN ,  Sang Hyun HAN ,  Guh Hwan LIM ,  Yo Han SONG ,  Dong Keun LEE ,  Kyeong Yub JUNG ,  Eun Gyu JEONG ,  Yu Mi KIM

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/42

CPC classification number: H05K1/0298 ,  H05K3/108 ,  H05K3/425 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A printed circuit board includes: a first insulating layer; a via pad disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a via hole exposing at least a portion of an upper surface of the via pad; a conductor pattern disposed on the exposed upper surface of the via pad; and a via including a first metal layer covering at least a portion of each of a wall surface of the via hole, the exposed upper surface of the via pad, and the conductor pattern, and a second metal layer disposed on the first metal layer and disposed in at least a portion of the via hole.