MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

    公开(公告)号:US20220189690A1

    公开(公告)日:2022-06-16

    申请号:US17552786

    申请日:2021-12-16

    Abstract: A multilayer capacitor includes a capacitor body having first to sixth surfaces, including a plurality of first and second dielectric layers and a plurality of internal electrodes stacked; and first and second external electrodes. The internal electrode includes first and second internal electrodes, a first floating electrode disposed between the first and second internal electrodes on the first dielectric layer, and second and third floating electrodes disposed on the second dielectric layer. The second floating electrode overlaps a portion of the first internal electrode and a portion of the first floating electrode, and the third floating electrode overlaps a portion of the second internal electrode and a portion of the first floating electrode. a/L is 0.113 or more, in which L is a length of the capacitor body, and a is a distance between the first floating electrode and the first or second internal electrodes.

    MULTILAYER ELECTRONIC COMPONENT
    2.
    发明申请

    公开(公告)号:US20220148804A1

    公开(公告)日:2022-05-12

    申请号:US17403161

    申请日:2021-08-16

    Abstract: A multilayer electronic component includes: a body including dielectric layers and internal electrodes alternately stacked with one of the dielectric layers interposed therebetween; and external electrodes disposed on external surfaces of the body and connected to the internal electrodes. One of the internal electrodes includes a plurality of conductive particles and conductive nanowires each of which having a shape different from a shape of the plurality of conductive particles and being connected to at least one of the plurality of conductive particles.

    Multilayer capacitor and board having the same mounted thereon

    公开(公告)号:US11869718B2

    公开(公告)日:2024-01-09

    申请号:US17552786

    申请日:2021-12-16

    Abstract: A multilayer capacitor includes a capacitor body having first to sixth surfaces, including a plurality of first and second dielectric layers and a plurality of internal electrodes stacked; and first and second external electrodes. The internal electrode includes first and second internal electrodes, a first floating electrode disposed between the first and second internal electrodes on the first dielectric layer, and second and third floating electrodes disposed on the second dielectric layer. The second floating electrode overlaps a portion of the first internal electrode and a portion of the first floating electrode, and the third floating electrode overlaps a portion of the second internal electrode and a portion of the first floating electrode. a/L is 0.113 or more, in which L is a length of the capacitor body, and a is a distance between the first floating electrode and the first or second internal electrodes.

    Lead pin for package substrate
    5.
    发明授权
    Lead pin for package substrate 有权
    封装基板引脚

    公开(公告)号:US09142499B2

    公开(公告)日:2015-09-22

    申请号:US14302045

    申请日:2014-06-11

    Abstract: A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.

    Abstract translation: 用于封装衬底的引脚包括:连接销插入形成在外部衬底中的孔中; 形成在连接销的一端的头部; 以及形成在头部的一个表面上的阻挡部分,以便阻止焊膏的路径,使得当头部安装在头部上时,防止焊膏流过以覆盖头部的上部 封装衬底。

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