公开(公告)号：US09252212B2

公开(公告)日：2016-02-02

申请号：US14243873

申请日：2014-04-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  Ji Hye Kim ,  Kyu Hyun Mo ,  Dong Soo Seo ,  In Hyuk Song

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/1095 ,  H01L29/7397

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.

Abstract translation: 功率半导体器件可以包括：有源区域，其中电流流过当器件导通时形成的沟道; 设置在所述有源区域周围的端接区域; 第一导电类型的第一半导体区域，设置在从所述有源区域到所述端接区域的方向上的所述端接区域中; 以及第二导电类型的第二半导体区域，其设置在从所述有源区域到所述端接区域的方向上的所述端接区域中，所述第一半导体区域和所述第二半导体区域交替布置。

公开(公告)号：US09502498B2

公开(公告)日：2016-11-22

申请号：US14617158

申请日：2015-02-09

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyu Hyun Mo ,  Dong Soo Seo ,  Chang Su Jang ,  Jae Hoon Park ,  In Hyuk Song

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract translation: 功率半导体器件可以包括第一导电类型半导体衬底，设置在第一导电类型半导体衬底上的超接合部分，并且包括交替排列的第一导电型柱和第二导电型柱，并且三维 （3D）门部分，设置在第一导电型柱上。 3D栅极部分设置在第一导电型柱上以减小第一和第二导电型柱的宽度，从而有效地减小了器件尺寸。

公开(公告)号：US20150187869A1

公开(公告)日：2015-07-02

申请号：US14272009

申请日：2014-05-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  Kyu Hyun Mo ,  Jae Kyu Sung ,  Kee Ju Um ,  In Hyuk Song

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7813

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a resurf region disposed in the first semiconductor region and including first conductivity-type second semiconductor regions and second conductivity-type third semiconductor regions alternately disposed in a width direction; a first conductivity-type first cover region disposed in the first semiconductor region, disposed to be contiguous with an upper surface of the resurf region, and having an impurity concentration higher than that of the first semiconductor region; a second conductivity-type fourth semiconductor region disposed above the first semiconductor region; a first conductivity-type fifth semiconductor region disposed on an inner side of an upper portion of the fourth semiconductor region; and a trench gate disposed to penetrate from the fifth semiconductor region to a portion of an upper portion of the first semiconductor region and including a gate insulating layer and a conductive material.

Abstract translation: 功率半导体器件可以包括：第一导电类型的第一半导体区域; 设置在所述第一半导体区域中并且包括在宽度方向上交替布置的第一导电类型的第二半导体区域和第二导电类型的第三半导体区域的再生区域; 设置在所述第一半导体区域中的第一导电类型的第一覆盖区域，被设置为与所述复原区域的上表面邻接，并且具有高于所述第一半导体区域的杂质浓度的杂质浓度; 设置在所述第一半导体区域上方的第二导电型第四半导体区域; 设置在第四半导体区域的上部的内侧的第一导电型第五半导体区域; 以及沟槽栅极，设置成从第五半导体区域穿透到第一半导体区域的上部的一部分，并且包括栅极绝缘层和导电材料。

公开(公告)号：US09209287B2

公开(公告)日：2015-12-08

申请号：US14271075

申请日：2014-05-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  Ji Hye Kim ,  Kyu Hyun Mo ,  Ji Yeon Oh ,  Dong Soo Seo

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region.

Abstract translation: 功率半导体器件可以包括：第一导电类型的第一半导体区域; 设置在所述第一半导体区域上方的第二导电型第二半导体区域; 穿过所述第二半导体区域的沟槽栅极和所述第一半导体区域的一部分; 第三半导体区域，设置在所述沟槽栅极的两侧，并且设置在所述第二半导体区域的上部的内侧; 以及设置在第三半导体区域中的器件保护区域。

公开(公告)号：US20150179825A1

公开(公告)日：2015-06-25

申请号：US14332958

申请日：2014-07-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Kyu SUNG ,  Chang Su Jang ,  In-Hyuk Song ,  Kyu Hyun Mo ,  Sun Jae Yoon

IPC: H01L29/861 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/36 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/8611

Abstract: A diode device may include a first conductivity type first semiconductor region, a second conductivity type second semiconductor region partially formed inside an upper portion of the first semiconductor region, and second conductivity type third semiconductor regions partially formed inside the upper portion of the first semiconductor region, formed on sides of the second semiconductor region, and having an impurity concentration higher than that of the second semiconductor region.

Abstract translation: 二极管器件可以包括第一导电类型的第一半导体区域，部分地形成在第一半导体区域的上部内的第二导电类型的第二半导体区域，以及部分地形成在第一半导体区域的上部内的第二导电类型的第三半导体区域 形成在第二半导体区域的侧面上，其杂质浓度高于第二半导体区域的杂质浓度。