公开(公告)号：US09245986B2

公开(公告)日：2016-01-26

申请号：US14322346

申请日：2014-07-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo ,  Chang Su Jang

IPC: H01L29/78 ,  H01L29/00 ,  H01L21/336 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L29/36

CPC classification number: H01L29/7397 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/36 ,  H01L29/66348

Abstract: A power semiconductor device may include: a base substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract translation: 功率半导体器件可以包括：基底衬底，其包括第一导电型漂移层; 设置在所述基底基板的另一个表面上的第二导电型半导体基板; 第一导电型扩散层，设置在所述基底衬底中，其杂质浓度高于所述漂移层的杂质浓度; 设置在所述基底基板的一个表面内的第二导电型阱层; 从包括所述阱层的所述基底基板的一个表面形成的沟槽，以在深度方向上穿过所述扩散层; 设置在所述基底基板的表面上的第一绝缘膜; 以及设置在沟槽中的第一电极。 扩散层在横向上的杂质掺杂浓度的峰值点可以位于与沟槽的侧表面接触的区域中。

公开(公告)号：US20140159106A1

公开(公告)日：2014-06-12

申请号：US13874038

申请日：2013-04-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju UM ,  Dong Soo Seo ,  Chang Su Jang ,  In Hyuk Song ,  Jaehoon Park

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/423 ,  H01L29/66333

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括：第一导电型漂移层，形成在漂移层的边缘的上部上的第二导电型端接层和形成在侧面的高浓度第一导电型沟道阻挡层 漂移层边缘的表面。

公开(公告)号：US20150144994A1

公开(公告)日：2015-05-28

申请号：US14329378

申请日：2014-07-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Kyu SUNG ,  Dong Soo SEO ,  Chang Su Jang ,  Jae Hoon PARK ,  In Hyuk SONG

IPC: H01L29/739 ,  H01L29/417

CPC classification number: H01L29/7397 ,  H01L29/4232

Abstract: A power semiconductor device may include: a first semiconductor layer having a first conductivity type; a second semiconductor layer formed on the first semiconductor layer, having a concentration of impurities higher than that of the first semiconductor layer, and having the first conductivity type; a third semiconductor layer formed on the second semiconductor layer and having a second conductivity type; a fourth semiconductor layer formed in an upper surface of the third semiconductor layer and having the first conductivity type; and trench gates penetrating from the fourth semiconductor layer into a portion of the first semiconductor layer and having gate insulating layers formed on surfaces thereof. The trench gates have a first gate, a second gate, and a third gate are sequentially disposed from a lower portion thereof, and the first gate, the second gate, and the third gate are insulated from each other by gate insulating films.

Abstract translation: 功率半导体器件可以包括：具有第一导电类型的第一半导体层; 形成在第一半导体层上的第二半导体层，其杂质浓度高于第一半导体层，其具有第一导电类型; 形成在第二半导体层上并具有第二导电类型的第三半导体层; 形成在第三半导体层的上表面并具有第一导电类型的第四半导体层; 以及从第四半导体层穿入第一半导体层的一部分并且在其表面上形成有栅极绝缘层的沟槽栅极。 沟槽栅极具有第一栅极，第二栅极和第三栅极，从其下部依次配置，并且第一栅极，第二栅极和第三栅极通过栅极绝缘膜彼此绝缘。

公开(公告)号：US20150144993A1

公开(公告)日：2015-05-28

申请号：US14292297

申请日：2014-05-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Jae Hoon Park ,  Chang Su Jang ,  Ji Yeon Oh

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0661 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/7397

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; a termination region formed in the vicinity of the active region; a plurality of first trenches formed lengthwise in one direction in the active region; and at least one or more second trenches formed lengthwise in one direction in the termination region. The second trench has a depth deeper than that of the first trench.

Abstract translation: 功率半导体器件可以包括：在功率半导体器件的导通操作时具有流过其中形成的沟道的电流的有源区; 形成在有源区附近的端接区域; 多个第一沟槽，在有源区域中沿一个方向纵向形成; 以及至少一个或多个第二沟槽，其在端接区域中沿一个方向纵向形成。 第二沟槽的深度比第一沟槽深。

公开(公告)号：US20140117374A1

公开(公告)日：2014-05-01

申请号：US13758946

申请日：2013-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  Chang Su Jang ,  In Hyuk Song ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/20 ,  H01L29/00

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode.

Abstract translation: 本文公开了一种半导体器件，包括：基底; 形成在所述基底基板上的第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 阴极，形成在所述第二氮化物半导体层的一侧上; 具有一端和另一端的阳极，一端在第二氮化物半导体层的另一侧凹入达预定深度，另一端与阴极间隔开并形成为延伸至 阴极电极的上部; 以及在阳极电极和阴极电极之间形成在第二氮化物半导体层上以覆盖阴极电极的绝缘膜。

公开(公告)号：US09318589B2

公开(公告)日：2016-04-19

申请号：US13751916

申请日：2013-01-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon Park ,  Chang Su Jang ,  In Hyuk Song ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/739 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/1095

Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.

Abstract translation: 提供了一种绝缘栅双极晶体管，包括：第一导电类型的第一半导体区域; 形成在第一半导体区域的一个表面上的第二导电类型的第二半导体区域; 在第二半导体区域的一个表面上沿长度方向连续形成的第一导电类型的第三半导体区域; 多个沟槽，形成在第三半导体区域之间，延伸到第二半导体区域的内部，并且在长度方向上是连续的; 形成在第三半导体区域的一个表面上的第二导电类型的第四半导体区域，形成在沟槽内的绝缘层; 掩埋在绝缘层内的栅电极; 以及形成在与所述第二半导体区域内的所述第三半导体区域对应的位置中的至少一个的阻挡层。

公开(公告)号：US20150187678A1

公开(公告)日：2015-07-02

申请号：US14270894

申请日：2014-05-06

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jae Hoon PARK ,  Sun Jae Yoon ,  Chang Su Jang ,  Kee Ju Um ,  In Hyuk Song

IPC: H01L23/373

CPC classification number: H01L23/367 ,  H01L29/0834 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor layer; a second conductivity-type second semiconductor layer disposed above the first semiconductor layer; and a heat dissipation trench disposed to penetrate from an upper surface of the second semiconductor layer into a portion of the second semiconductor layer and having an insulating layer disposed on a surface thereof.

Abstract translation: 功率半导体器件可以包括：第一导电型第一半导体层; 设置在所述第一半导体层上方的第二导电型第二半导体层; 以及散热沟，其设置成从所述第二半导体层的上表面穿透到所述第二半导体层的一部分中，并且具有设置在其表面上的绝缘层。

公开(公告)号：US08969959B2

公开(公告)日：2015-03-03

申请号：US13795414

申请日：2013-03-12

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Chang Su Jang

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L29/0638 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/66136 ,  H01L29/8611

Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括第一导电类型的体层; 第二导电类型的有源层，与主体层的上部接触; 以及形成在有源层的上部的第一导电类型的场限制环。

公开(公告)号：US09184247B2

公开(公告)日：2015-11-10

申请号：US13795858

申请日：2013-03-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Kee Ju Um ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/732 ,  H01L29/739 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/7397

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract translation: 这里公开了功率半导体器件。 功率半导体器件包括形成为与第二导电类型阱层的一侧接触的第二导电型第一结端接延伸（JTE）层，形成在其上的第二导电型第二JTE层 线作为第二导电型第一JTE层，并且形成为在基板的长度方向上与第二导电型第一JTE层间隔开，并且形成为与第二导电型第一JTE层接触的多晶硅层 第二导电类型阱层和第二导电型第一JTE层的上部。

公开(公告)号：US09153678B2

公开(公告)日：2015-10-06

申请号：US13871082

申请日：2013-04-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Chang Su Jang ,  Jaehoon Park ,  Dong Soo Seo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract translation: 提供了一种功率半导体器件，包括形成在有源区中的触点，从第一区延伸形成第一终端区并与触点交替形成的沟槽栅，形成在有源区的触点和 沟槽栅极，形成在第一端接区域中的第一导电阱延伸部分和第二端接区域的一部分，以及形成在第二端接区域中并接触阱延伸部分的第一导电场限制环。