公开(公告)号：US20250022860A1

公开(公告)日：2025-01-16

申请号：US18436034

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chengtar Wu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package according to an embodiment includes an interposer including a power distribution structure, and a redistribution structure on the power distribution structure; a first semiconductor die on the interposer; and a second semiconductor die on the interposer, wherein the power distribution structure may include a power distribution module connected to the bottom surface of the redistribution structure; a plurality of conductive posts connected to the bottom surface of the redistribution structure; and a molding material for molding the power distribution module and the plurality of conductive posts.

公开(公告)号：US20240421123A1

公开(公告)日：2024-12-19

申请号：US18406800

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chengtar Wu ,  CHOONGBIN YIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

Abstract: A semiconductor package includes: a substrate; a first semiconductor structure on the substrate, wherein the first semiconductor structure includes a first redistribution layer structure and a first semiconductor die that is disposed on the first redistribution layer structure and includes a plurality of first through-semiconductor vias; a second semiconductor structure disposed side by side with the first semiconductor structure on the substrate, wherein the second semiconductor structure includes a second redistribution layer structure and a second semiconductor die that is disposed on the second redistribution layer structure and includes a plurality of second through-semiconductor vias; a plurality of bonding wires electrically connecting the first semiconductor die and the second semiconductor die on the first semiconductor die and the second semiconductor die; and a molding material surrounding the plurality of bonding wires and through which the plurality of bonding wires pass.

公开(公告)号：US20240395781A1

公开(公告)日：2024-11-28

申请号：US18407893

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chengtar Wu

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/522 ,  H10B80/00

Abstract: A semiconductor package according to an embodiment includes a first three-dimensional integrated circuit structure; and a second three-dimensional integrated circuit structure on the first three-dimensional integrated circuit structure, wherein the first three-dimensional integrated circuit structure includes a baseband die; and a memory die on the baseband die, the second three-dimensional integrated circuit structure includes a transceiver die; and a radio communication die on the transceiver die, and the radio communication die includes one or more metal patterns on an upper surface thereon.

公开(公告)号：US20240404921A1

公开(公告)日：2024-12-05

申请号：US18439461

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Chengtar Wu

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a redistribution layer structure; first semiconductor and second dies on the redistribution, the second semiconductor die positioned next to the first semiconductor die; core balls positioned on the redistribution structure and next to the first semiconductor chip die; a bridge die configured to electrically connect the first and second semiconductor dies to each other on the first and second semiconductor dies; a substrate including an upper plate portion and a sidewall portion, the upper plate portion and the sidewall portion defining a cavity, the upper plate portion positioned on the bridge die, the side wall portion positioned on the core balls, the bridge die positioned within the cavity; and a molding material configured to mold the first semiconductor die, the second semiconductor die, the core balls, and the bridge die between the redistribution layer structure and the substrate.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

Abstract: A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US20250062260A1

公开(公告)日：2025-02-20

申请号：US18608838

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD,

Inventor： CHOONGBIN YIM ,  JONGKOOK KIM ,  Chengtar Wu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a second semiconductor chip disposed on the first semiconductor chip; a passive component disposed on the first semiconductor chip; and an encapsulant that encapsulates the second semiconductor chip and the passive component. The first semiconductor chip includes a first through via that extends through at least a portion of the first semiconductor chip, and a first pad disposed on a first surface thereof and connected to the first through via. The passive component includes at least one trench and a second pad disposed on a first surface thereof and connected to the trench. The first pad and the second pad are directly bonded by contacting each other.