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1.发明申请XOR-BASED SCRAMBLER/DESCRAMBLER FOR SSD COMMUNICATION PROTOCOLS 审中-公开用于SSD通信协议的基于XOR的SCRAMBLER / DESCRAMBLER公开(公告)号：US20160328567A1
公开(公告)日：2016-11-10
申请号：US15064191
申请日：2016-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chihjen Chang , Michael Bekerman , Ian Swarbrick , Craig Hanson
Abstract: Example embodiments for descrambling and scrambling a memory channel comprise: executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data by: inputting all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device, such that the scrambled training data are equal to the XOR vectors corresponding to those memory locations; receiving the scrambled training data over memory channel by the memory device and storing the scrambled training data as the XOR vectors for each of the corresponding memory locations; and during a functional mode of the memory device, receiving the scrambled data over the memory channel for a specified memory location, and using the XOR vector stored for the specified memory location to descramble the scrambled data prior to writing to the specified memory location.
Abstract translation: 用于解扰和加扰存储器通道的示例性实施例包括：执行用于存储器设备的训练模式以发现由主机系统使用的XOR向量来加扰数据，方法是：将所有零训练数据输入到存储器设备的所有存储器位置的加扰算法 以产生通过存储器通道发送到存储器件的加扰训练数据，使得加扰的训练数据等于对应于那些存储器位置的XOR矢量; 通过存储器装置通过存储器通道接收加扰的训练数据，并将加扰的训练数据存储为每个对应的存储单元的XOR向量; 并且在存储器件的功能模式期间，通过存储器通道接收用于指定存储器位置的加扰数据，并且使用为指定存储器位置存储的XOR向量在写入指定的存储器位置之前解扰加扰数据。
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公开(公告)号：US10558388B2
公开(公告)日：2020-02-11
申请号：US15169609
申请日：2016-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng , Craig Hanson , Sun Young Lim , Indong Kim
IPC: G06F3/06
Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.
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Patent Agency Ranking
公开(公告)号：US20170255418A1
公开(公告)日：2017-09-07
申请号：US15169609
申请日：2016-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng , Craig Hanson , Sun Young Lim , Indong Kim
IPC: G06F3/06
Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies
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公开(公告)号：US10347306B2
公开(公告)日：2019-07-09
申请号：US15231629
申请日：2016-08-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mu-Tien Chang , Dimin Niu , Hongzhong Zheng , Craig Hanson , Sun Young Lim , Indong Kim , Jangseok Choi
IPC: G06F1/32 , G06F1/26 , G11C7/10 , G06F1/3234 , G11C5/04 , G11C7/22 , G06F1/3287 , G11C5/14 , G11C11/4074
Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.
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公开(公告)号：US12189546B2
公开(公告)日：2025-01-07
申请号：US17872987
申请日：2022-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng , Sun Young Lim , Indong Kim , Jangseok Choi , Craig Hanson
Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
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公开(公告)号：US12147360B2
公开(公告)日：2024-11-19
申请号：US17872987
申请日：2022-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng , Sun Young Lim , Indong Kim , Jangseok Choi , Craig Hanson
Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
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公开(公告)号：US10121013B2
公开(公告)日：2018-11-06
申请号：US15064191
申请日：2016-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chihjen Chang , Michael Bekerman , Ian Swarbrick , Craig Hanson
Abstract: Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.
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