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公开(公告)号:US20210248035A1
公开(公告)日:2021-08-12
申请号:US17239621
申请日:2021-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: KICHEOL EOM , JAEHO SIM , DONG-RYOUL LEE , HYUN JU YI , HYOTAEK LEEM
Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.
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2.
公开(公告)号:US20210257034A1
公开(公告)日:2021-08-19
申请号:US17307314
申请日:2021-05-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DONG-RYOUL LEE , HYUN JU YI , JAEHO SIM , KICHEOL EOM , HYOTAEK LEEM
Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.
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3.
公开(公告)号:US20200151040A1
公开(公告)日:2020-05-14
申请号:US16539729
申请日:2019-08-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DONG-RYOUL LEE , Hyun Ju Yi , Jaeho Sim , Kicheol Eom , Hyotaek Leem
Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.
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4.
公开(公告)号:US20230020537A1
公开(公告)日:2023-01-19
申请号:US17952370
申请日:2022-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DONG-RYOUL LEE , Hyun Ju Yi , Jaeho Sim , Kicheol Eom , Hyotaek Leem
Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.
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公开(公告)号:US20190036546A1
公开(公告)日:2019-01-31
申请号:US16116500
申请日:2018-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YONGWON CHO , HYNSOO BAE , HYOTAEK LEEM , DONG-RYOUL LEE , HYUN JU YI , TAEHACK LEE
Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.
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6.
公开(公告)号:US20210141440A1
公开(公告)日:2021-05-13
申请号:US17151273
申请日:2021-01-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUN JU YI , JAEHO SIM , KICHEOL EOM , DONG-RYOUL LEE , HYOTAEK LEEM
Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.
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公开(公告)号:US20200151055A1
公开(公告)日:2020-05-14
申请号:US16533894
申请日:2019-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: KICHEOL EOM , JAEHO SIM , DONG-RYOUL LEE , HYUN JU YI , HYOTAEK LEEM
Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.
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8.
公开(公告)号:US20190187774A1
公开(公告)日:2019-06-20
申请号:US16055197
申请日:2018-08-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUN JU YI , JAEHO SIM , KICHEOL EOM , DONG-RYOUL LEE , HYOTAEK LEEM
CPC classification number: G06F1/3275 , G06F13/1689 , G06F13/4243 , G06F13/4273 , G11C5/14 , G11C16/30 , G11C16/32
Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.
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