公开(公告)号：US20250107208A1

公开(公告)日：2025-03-27

申请号：US18976637

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20230187335A1

公开(公告)日：2023-06-15

申请号：US18105955

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee SEO ,  Heonbok LEE ,  Tae-Yeol KIM ,  Daeyong KIM ,  Dohyun LEE

IPC: H01L23/498 ,  H01L29/78

CPC classification number: H01L23/49844 ,  H01L29/78 ,  H01L23/49811

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

公开(公告)号：US20210167004A1

公开(公告)日：2021-06-03

申请号：US16893540

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghee SEO ,  Heonbok LEE ,  Tae-Yeol KIM ,  Daeyong KIM ,  Dohyun LEE

IPC: H01L23/498 ,  H01L29/78

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

公开(公告)号：US20170186758A1

公开(公告)日：2017-06-29

申请号：US15458273

申请日：2017-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

IPC: H01L27/11524 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157

CPC classification number: H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

公开(公告)号：US20230070266A1

公开(公告)日：2023-03-09

申请号：US17670949

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20200161179A1

公开(公告)日：2020-05-21

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun LEE ,  Youngwoo PARK ,  Junghoon PARK ,  Jaeduk LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.