公开(公告)号：US20150363106A1

公开(公告)日：2015-12-17

申请号：US14722158

申请日：2015-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young LIM ,  Dong-Yang LEE ,  Young-Jin CHO ,  Oh-Seong KWON

IPC: G06F3/06

CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Abstract translation: 电子设备包括存储器控制器; 耦合到所述存储器控制器的第一存储器件; 耦合到所述存储器控制器的第二存储器设备，所述第二存储器设备是与所述第一存储器设备不同类型的存储器; 以及存储器控制器和第二存储器件之间的转换电路。 存储器控制器被配置为根据第一定时方案向第一存储器设备发送第一命令和第一数据以访问第一存储器件，并且根据第一定时方案向转换电路发送第二命令和数据包到第 访问第二个存储设备。 转换电路被配置为接收第二命令和分组，并且基于第二命令和分组访问第二存储器设备。

公开(公告)号：US20160133314A1

公开(公告)日：2016-05-12

申请号：US14793749

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hee HWANG ,  Sang-Kyu KANG ,  Dong-Yang LEE ,  Jae-Yeon CHOI ,  Jong-Hyun CHOI

IPC: G11C11/406

CPC classification number: G11C11/40611 ,  G11C7/1063 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract translation: 半导体存储器件包括存储单元阵列和刷新控制电路。 存储单元阵列包括多个存储单元行。 刷新控制电路对多个存储单元行执行正常刷新操作，并对多个存储单元行的多个弱页执行弱刷新操作。 每个弱页包括至少一个数据保留时间小于正常单元的弱单元。 当刷新控制电路在正常访问模式下对弱页执行弱刷新操作时，刷新控制电路将刷新标志信号发送到半导体存储器件外部的存储器控​​制器。

公开(公告)号：US20150128000A1

公开(公告)日：2015-05-07

申请号：US14531250

申请日：2014-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Yun JUNG ,  Min-Yeab CHOO ,  Do-Geun KIM ,  Mi-Kyoung PARK ,  Dong-Yang LEE ,  Sun-Young LIM ,  Bu-Il JUNG ,  Hyuk HAN

IPC: G11C29/44 ,  G06F11/22

CPC classification number: G06F11/2268 ,  G11C16/20 ,  G11C2029/4402

Abstract: In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system.

Abstract translation: 在操作包括存储器设备和存储器控制器的存储器系统的方法中，存储器控制器从包括在存储器件中的故障信息区域读取故障信息。 存储器控制器基于故障信息将与程序相关的逻辑地址映射到安全区域的物理地址，以将程序存储在除了故障信息区域以外的安全区域和包括在存储器件中的故障区域。 存储器控制器根据地址映射将程序加载到存储器件的安全区域。 根据示例性实施例的操作存储器系统的方法增加了存储器系统的性能。

公开(公告)号：US20150169333A1

公开(公告)日：2015-06-18

申请号：US14530951

申请日：2014-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bu-Il JUNG ,  Ju-Yun JUNG ,  Do-Geun KIM ,  Dong-Yang LEE ,  Min-Yeab CHOO

IPC: G06F9/44 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/44 ,  G06F9/4401 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.

Abstract translation: 存储器系统包括只读存储器（ROM），主存储器和处理器。 ROM存储基本的输入/输出系统（BIOS）。 主存储器包括故障地址表，其存储指定具有至少一个缺陷单元的存储单元行的至少一个故障地址。 处理器从主存储器接收至少一个故障地址的故障信息，并且通过在与主存储器的安全区域相对应的故障区域中避免与至少一个故障地址相对应的故障区域来将与存储器系统的引导操作相关联的数据加载到主存储器的安全区域 电源被施加到存储器系统时的上电操作。 与引导操作相关联的数据存储在存储设备中。

公开(公告)号：US20160189787A1

公开(公告)日：2016-06-30

申请号：US15062546

申请日：2016-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeong-Han LEE ,  Seok-Cheon KWON ,  Dong-Yang LEE

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

公开(公告)号：US20150131393A1

公开(公告)日：2015-05-14

申请号：US14534492

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeab CHOO ,  Bu-Il JUNG ,  Do-Geun KIM ,  Mi-Kyoung PARK ,  Dong-Yang LEE ,  Sun-Young LIM ,  Ju-Yun JUNG ,  Hyuk HAN

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/04 ,  G11C29/78 ,  G11C29/785 ,  G11C29/88

Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Abstract translation: 一种修复包括引导存储器区域，正常存储器区域和冗余存储器区域的存储器件的方法，所述冗余存储器区域包括多个修复存储器单元，包括通过执行以下操作中的至少一个修复引导存储器区域：排除第一 引导存储器区域的故障存储器单元用作存储，并且用修复存储器单元的引导修复存储器单元替换第一故障存储器单元，每个第一故障存储器单元具有至少一个故障存储器单元; 并且在修复引导存储器区域之后，通过执行排除第二故障存储器单元中的至少一个作为存储来修复正常存储器区域，并用修复存储器单元的正常修复存储器单元替换第二故障存储器单元。