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公开(公告)号：US20210098460A1
公开(公告)日：2021-04-01
申请号：US16860276
申请日：2020-04-28
发明人： Sang Ho LEE , Eun A KIM , Ki Seok LEE , Jay-Bok CHOI , Keun Nam KIM , Yong Seok AHN , Jin-Hwan CHUN , Sang Yeon HAN , Sung Hee HAN , Seung Uk HAN , Yoo Sang HWANG
IPC分类号： H01L27/108 , H01L23/528
摘要： A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.
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公开(公告)号：US20240074146A1
公开(公告)日：2024-02-29
申请号：US18116475
申请日：2023-03-02
发明人： Eunjung KIM , Eun A KIM
CPC分类号： H10B12/315 , H10B12/0335 , H10B61/22 , H10B63/10 , H10B63/30
摘要： A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device includes an active pattern; a gate structure on the active pattern; a bit-line structure electrically connected to the active pattern; a storage node contact electrically connected to the active pattern; and a landing pad electrically connected to the storage node contact, wherein the landing pad includes a first pad flat sidewall and a second pad flat sidewall that are opposite to each other, a third pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a fourth pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a first pad curved sidewall between the first pad flat sidewall and the third pad flat sidewall, and a second pad curved sidewall between the first pad flat sidewall and the fourth pad flat sidewall.
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3.发明申请公开(公告)号：US20190172904A1
公开(公告)日：2019-06-06
申请号：US16268185
申请日：2019-02-05
发明人： Jong-Min LEE , Jongryul JUN , Eun A KIM , Jung-Bum LIM
IPC分类号： H01L49/02 , H01L27/08 , H01L27/108
摘要： Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
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公开(公告)号：US20210408004A1
公开(公告)日：2021-12-30
申请号：US17469340
申请日：2021-09-08
发明人： Sang Ho LEE , Eun A KIM , Ki Seok LEE , Jay-Bok CHOI , Keun Nam KIM , Yong Seok AHN , Jin-Hwan CHUN , Sang Yeon HAN , Sung Hee HAN , Seung Uk HAN , Yoo Sang HWANG
IPC分类号： H01L27/108 , H01L23/528
摘要： A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.
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公开(公告)号：US20240121947A1
公开(公告)日：2024-04-11
申请号：US18198980
申请日：2023-05-18
发明人： Eunjung KIM , Eun A KIM
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/485 , H10B12/488
摘要： A semiconductor device includes active patterns disposed on a substrate and including central portions, respectively, bit lines extending in a first direction on the central portions of the active patterns, word lines intersecting the active patterns in a second direction intersecting the first direction, fence patterns disposed between the bit lines adjacent to each other on the word lines, a contact trench region intersecting the active patterns and the word lines in a third direction intersecting the first and second directions, and bit line contacts and filling insulation patterns alternately arranged in the third direction in the contact trench region. The first to third directions are parallel to a bottom surface of the substrate. The filling insulation patterns are disposed between the word lines and the fence patterns, respectively.
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