公开(公告)号：US20150179574A1

公开(公告)日：2015-06-25

申请号：US14618837

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

IPC: H01L23/528 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

Abstract translation: 根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。 此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。 结果，可以抑制掩模未对准的发生。

公开(公告)号：US20240268129A1

公开(公告)日：2024-08-08

申请号：US18370940

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jay-Bok CHOI ,  Hyungeun CHOI ,  Jinwoo HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

公开(公告)号：US20210408004A1

公开(公告)日：2021-12-30

申请号：US17469340

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US20220028868A1

公开(公告)日：2022-01-27

申请号：US17192069

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyewon KIM ,  Eunjung KIM ,  Geumjung SEONG ,  Jay-Bok CHOI

IPC: H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region therebetween, a cell device isolation pattern on the cell region of the substrate to define cell active patterns, a peripheral device isolation pattern on the peripheral region of the substrate to define peripheral active patterns, and an insulating isolation pattern on the boundary region of the substrate, the insulating isolation pattern being between the cell active patterns and the peripheral active patterns, wherein a bottom surface of the insulating isolation pattern includes a first edge adjacent to a side surface of a corresponding one of the cell active patterns, and a second edge adjacent to a side surface of a corresponding one of the peripheral active patterns, the first edge being at a height lower than the second edge, when measured from a bottom surface of the substrate.

公开(公告)号：US20210118886A1

公开(公告)日：2021-04-22

申请号：US16887297

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jay-Bok CHOI ,  Su Ji AHN ,  Yong Seok AHN ,  Seung Hyung LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a cell region, a boundary region, a peripheral region sequentially arranged in a first direction, an active pattern extending in the cell region in a second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region and directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending in a third direction, which is perpendicular to the first direction, from the first side surface, and the first boundary surface defines a boundary between the cell region and the boundary region.

公开(公告)号：US20210098460A1

公开(公告)日：2021-04-01

申请号：US16860276

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.