公开(公告)号：US20240128145A1

公开(公告)日：2024-04-18

申请号：US18469111

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONSEOK LEE ,  DONGKYU KIM ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L21/306 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3738 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/95 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15174 ,  H01L2924/3511

Abstract: A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.

公开(公告)号：US20230361017A1

公开(公告)日：2023-11-09

申请号：US18119705

申请日：2023-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJEONG HWANG ,  INHYUNG SONG ,  HYEONSEOK LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/544 ,  H01L21/565 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2223/54486 ,  H01L2924/1533 ,  H01L2924/15165

Abstract: Disclosed are packages and their fabrication methods. The package includes: a lower substrate with an upper pad; a lower chip on the lower substrate; a mold layer on the lower chip and the lower substrate; a post extending through the mold layer and provided on the upper pad around the lower chip, the post having a diameter less than a diameter of the upper pad; and an upper substrate on the post and the mold layer, the upper substrate including a lower pad having a diameter greater than the diameter of the post.