公开(公告)号：US20140357062A1

公开(公告)日：2014-12-04

申请号：US14290171

申请日：2014-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong-Han SHIN ,  Bong-Jin KUH ,  Tae-Gon KIM ,  Han-Mei CHOI ,  Jeong-Meung KIM

IPC: H01L21/02

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12169

Abstract: A method of fabricating a semiconductor device, the method including forming a trench on a substrate; forming an insulating layer pattern within the trench; depositing an amorphous material on the substrate and the insulating layer pattern; planarizing the amorphous material; removing a portion of the amorphous material, the removed portion of the amorphous material being on an area of the substrate where the trench has been formed; crystallizing remaining portions of the amorphous material into a single crystal material; and planarizing the single crystal material.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成沟槽; 在沟槽内形成绝缘层图案; 在基板和绝缘层图案上沉积非晶材料; 平面化无定形材料; 去除所述非晶材料的一部分，所述非晶材料的去除部分位于已经形成所述沟槽的所述衬底的区域上; 将所述无定形材料的剩余部分结晶成单晶材料; 并平面化单晶材料。

公开(公告)号：US20150372194A1

公开(公告)日：2015-12-24

申请号：US14764513

申请日：2014-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Nam-Goo CHA ,  Bong-Jin KUH ,  Han-Mei CHOI

IPC: H01L33/24 ,  H01L33/18 ,  H01L33/20

CPC classification number: H01L33/24 ,  B82Y20/00 ,  H01L33/005 ,  H01L33/08 ,  H01L33/18 ,  H01L33/20

Abstract: There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer.

Abstract translation: 提供一种纳米结构半导体发光器件，其包括由第一导电型半导体形成的基极层，设置在基底层上的第一绝缘层，并且具有暴露基底层的部分区域的多个第一开口，多个纳米孔 设置在所述基底层的所述露出区域中并且由所述第一导电型半导体形成，所述有源层设置在所述多个纳米孔的位于比所述第一绝缘层高的表面上;第二绝缘层，设置在所述第一绝缘层上 并且具有围绕所述多个纳米孔的多个第二开口和设置在所述多个纳米孔的表面上的所述有源层，以及设置在所述有源层的表面上的第二导电类型半导体层，所述第二导电类型半导体层被定位成高于所述第二绝缘体 层。

公开(公告)号：US20140357071A1

公开(公告)日：2014-12-04

申请号：US14276213

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Young JO ,  Jong-Hoon KANG ,  Tae-Gon KIM ,  Han-Mei CHOI

IPC: H01L21/28

CPC classification number: H01L21/28035 ,  H01L21/2255 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/66575

Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

Abstract translation: 可以提供制造具有掺杂层的半导体器件的方法。 该方法包括提供具有第一区域和第二区域的衬底，在衬底上形成栅极电介质层，在栅极电介质层上形成第一栅电极层，在第一栅电极层上形成第一掺杂层，形成第 在所述第一掺杂层上形成第一覆盖层，在所述第一区域中的所述第一覆盖层上形成掩模图案，所述掩模图案在所述第二区域中暴露所述第一覆盖层，在所述第二区域中去除所述第一覆盖层和所述第一掺杂层 去除所述掩模图案，以及在所述第一区域中的所述第一覆盖层和所述第二区域中的所述第一栅极电极层上形成第二掺杂层。

公开(公告)号：US20130170784A1

公开(公告)日：2013-07-04

申请号：US13726346

申请日：2012-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Chul KIM ,  Bong-Jin KUH ,  Jung-Yun WON ,  Eun-Ha LEE ,  Han-Mei CHOI

IPC: G02B6/122 ,  G02F1/035 ,  G02B6/124

CPC classification number: G02B6/13 ,  G02B6/122 ,  G02B6/124 ,  G02B6/131 ,  G02B6/132 ,  G02B2006/12061 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12147 ,  G02F1/025 ,  G02F1/035 ,  H01L29/66477

Abstract: A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation .