公开(公告)号：US20170358680A1

公开(公告)日：2017-12-14

申请号：US15420512

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon JEONG ,  Hong Bum PARK ,  HanMei CHOI ,  Jae Young PARK ,  Seung Hyun LIM

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

公开(公告)号：US20180331119A1

公开(公告)日：2018-11-15

申请号：US16027667

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho KIM ,  BiO KIM ,  Hyung Joon KIM ,  Young Seon SON ,  Su Jin SHIN ,  Jae Young AHN ,  Ju Mi YUN ,  HanMei CHOI

IPC: H01L27/11582 ,  H01L29/792 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/7926

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.