公开(公告)号：US09899594B2

公开(公告)日：2018-02-20

申请号：US15169775

申请日：2016-06-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ki-Woong Kim ,  Ju-Hyun Kim ,  Yong-Sung Park ,  Se-Chung Oh ,  Joon-Myoung Lee

IPC分类号： H01L29/94 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

CPC分类号： H01L43/10 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic memory device includes a substrate, a circuit device on the substrate, a lower electrode electrically connected to the circuit device, a magnetic tunnel junction structure (MTJ structure) on the lower electrode, and an upper electrode on the MTJ structure. The MTJ structure includes a pinned layer structure including at least one crystalline ferromagnetic layer and at least one amorphous ferromagnetic layer, a free layer, and a tunnel barrier layer between the pinned layer structure and the free layer.

公开(公告)号：US09666789B2

公开(公告)日：2017-05-30

申请号：US14741446

申请日：2015-06-16

申请人： Samsung Electronics Co., Ltd.

发明人： Jeong-Heon Park ,  Ki-Woong Kim ,  Hee-Ju Shin ,  Joon-Myoung Lee ,  Woo-Jin Kim ,  Jae-Hoon Kim ,  Se-Chung Oh ,  Yun-Jae Lee

IPC分类号： H01L43/02 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01L23/528 ,  H01L27/22 ,  H01F10/30

CPC分类号： H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

公开(公告)号：US20190081102A1

公开(公告)日：2019-03-14

申请号：US15919639

申请日：2018-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： Kichul Park ,  Ki-Woong Kim ,  Hansol Seok ,  Byoungho Kwon ,  Boun Yoon

IPC分类号： H01L27/22 ,  H01L23/522 ,  H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L23/532 ,  H01L23/528 ,  G11C11/16 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

摘要： A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.