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    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220085016A1

    公开(公告)日：2022-03-17

    申请号：US17533212

    申请日：2021-11-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joong Gun OH ,  Sung Il PARK ,  Jae Hyun PARK ,  Hyung Suk LEE ,  Eun Sil PARK ,  Yun Il LEE

    IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160148944A1

    公开(公告)日：2016-05-26

    申请号：US14919083

    申请日：2015-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tea Kwang YU ,  Yong Tae KIM ,  Jae Hyun PARK ,  Kyong Sik YEOM

    IPC: H01L27/115

    CPC classification number: H01L27/11536 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

    Abstract: A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.

    Abstract translation: 半导体器件的制造方法可以包括在包括单元区域的基板的单元区域和与单元区域相邻的逻辑区域中形成包括浮置栅电极层和控制栅极电极层的分割栅极结构。 该方法可以包括在逻辑区域和单元区域中顺序地形成第一栅极绝缘膜和金属栅极膜，从单元区域和逻辑区域的至少一部分去除金属栅极膜，形成第二栅极绝缘膜 在去除了金属栅极膜的第一栅极绝缘膜上，在逻辑区域和单元区域上形成栅电极膜，并且形成设置在单元区域中的多个存储单元元件和设置在多个电路元件中的多个电路元件 在逻辑区域。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250040241A1

    公开(公告)日：2025-01-30

    申请号：US18430457

    申请日：2024-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Il PARK ,  Jae Hyun PARK ,  Jin Wook YANG

    IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: A semiconductor device includes a first active pattern extending in a first direction, a second active pattern on the first active pattern and extending in the first direction, a gate structure on the first active pattern and the second active pattern and extending in a second direction intersecting the first direction, a first source/drain region on side faces of the gate structure and connected to the first active pattern, a second source/drain region on the side faces of the gate structure and connected to the second active pattern, and an intermediate connecting layer which includes a first intermediate conductive pattern between the first active pattern and the second active pattern, and a second intermediate conductive pattern connected to the first intermediate conductive pattern between the first source/drain region and the second source/drain region.

    ANALOG FRONT-END RECEIVER AND ELECTRONIC DEVICE INCLUDING THE SAME RECEIVER
    8.
    发明申请
    ANALOG FRONT-END RECEIVER AND ELECTRONIC DEVICE INCLUDING THE SAME RECEIVER 有权

    公开(公告)号：US20220141056A1

    公开(公告)日：2022-05-05

    申请号：US17461070

    申请日：2021-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byeong Gyu PARK ,  Jun Han BAE ,  Yun Guen NAM ,  Jae Hyun PARK ,  Gyeong Seok SONG ,  Ho-Bin SONG

    IPC: H04L25/03 ,  H03F3/45 ,  H04B3/08 ,  H04B1/18

    Abstract: An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.

    APPARATUS RELATED TO METRIC-LEARNING-BASED DATA CLASSIFICATION AND METHOD THEREOF
    9.
    发明申请
    APPARATUS RELATED TO METRIC-LEARNING-BASED DATA CLASSIFICATION AND METHOD THEREOF 审中-公开

    公开(公告)号：US20200257975A1

    公开(公告)日：2020-08-13

    申请号：US16760181

    申请日：2017-12-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae Kwon CHANG ,  In Kwon CHOI ,  Jae Hyun PARK

    IPC: G06N3/08 ,  G06F40/30 ,  G06N3/04

    Abstract: The present invention provides artificial intelligence technology which has machine-learning-based information understanding capability, including metric learning providing improved classification performance, classification of an object considering a semantic relationship, understanding of the meaning of a scene based on the metric learning and the classification, and the like. An electronic device according to one embodiment of the present invention comprises a memory in which at least one instruction is stored, and a processor for executing the stored instruction. Here, the processor extracts feature data from training data of a first class, obtains a feature point by mapping the extracted feature data to an embedding space, and makes an artificial neural network learn in a direction for reducing a distance between the obtained feature point and an anchor point.

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