公开(公告)号：US20140209976A1

公开(公告)日：2014-07-31

申请号：US14163972

申请日：2014-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Jae Yang ,  Sang-Su KIM ,  Jung-Dal CHOI ,  Sung-Gi HUR

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract translation: 公开了晶体管及其制造方法。 晶体管包括第一外延层，沟道层，栅极结构和杂质区。 衬底上的第一外延层包括具有大于锗（Ge）单晶的晶格常数的晶格常数的硅 - 锗 - 锡（SixGe1-x-ySny）单晶。 沟道层设置成与第一外延层相邻。 沟道层包括锗单晶。 栅极结构设置在沟道层上。 杂质区设置在与栅极结构相邻的沟道层的上部。

公开(公告)号：US20150035009A1

公开(公告)日：2015-02-05

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae YANG ,  Sang-Su KIM ,  Jae-Hwan LEE ,  Jung-Dal CHOI

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。

公开(公告)号：US20130214413A1

公开(公告)日：2013-08-22

申请号：US13769493

申请日：2013-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sok-Won LEE ,  Joon-Hee LEE ,  Jung-Dal CHOI ,  Seong-Min JO

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L23/4821 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/764 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/4827 ,  H01L23/52 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.

公开(公告)号：US20130175663A1

公开(公告)日：2013-07-11

申请号：US13728785

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Kwan YOU ,  Seung-Woo PAEK ,  Chung-II HYUN ,  Jung-Dal CHOI

IPC: H01L27/10

CPC classification number: H01L27/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66636

Abstract: A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.

Abstract translation: 半导体存储器件包括设置在半导体器件中沿第一方向延伸并具有与半导体衬底相同的第一晶体方向的隔离沟槽之间的线状图案。 桥模式连接至少两个相邻的线状图案，并且包括具有与第一晶体方向不同的第二晶体方向的半导体材料。 第一隔离层图案设置在半导体衬底的场区域中的至少一个隔离沟槽中。 存储单元被布置在至少一个线性图案上。

公开(公告)号：US20150061132A1

公开(公告)日：2015-03-05

申请号：US14532484

申请日：2014-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sok-Won LEE ,  Joon-Hee LEE ,  Jung-Dal CHOI ,  Seong-Min JO

IPC: H01L23/482 ,  H01L21/768

CPC classification number: H01L23/4821 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/764 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/4827 ,  H01L23/52 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.

Abstract translation: 导电线结构及其形成方法包括第一和第二图案结构，绝缘层图案和绝缘夹层。 第一图案结构包括导线图案和硬掩模，并且沿第一方向延伸。 第二图案结构包括第二导电线图案和另一个硬掩模，并且图案结构的至少一部分沿第一方向延伸。 绝缘层图案接触图形结构的端部。 第一图案结构和绝缘层图案在平面图中形成闭合曲线形状，并且第二图案结构和另一绝缘层图案在平面图中形成另一封闭曲线形状。 绝缘中间层覆盖图案结构的上部和绝缘层图案，图案结构之间的空气间隙和绝缘层图案之间的另一气隙。

公开(公告)号：US20140183615A1

公开(公告)日：2014-07-03

申请号：US14163228

申请日：2014-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Hyung Kim ,  Sung-II CHANG ,  Chang-Seok KANG ,  Jung-Dal CHOI

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11529 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7883

Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Abstract translation: 非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。 可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。 可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。 此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。 可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。 还讨论了相关方法。

公开(公告)号：US20140159137A1

公开(公告)日：2014-06-12

申请号：US14177693

申请日：2014-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Jung-Dal CHOI ,  Kwang-Soo SEOL

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

Abstract: A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.

Abstract translation: 非易失性存储器件的栅极结构及其形成方法，其包括隧道氧化物层图案，电荷陷阱层图案，阻挡介电层图案，其最上层包括第一介电常数大于其的介电常数的材料。 包括在隧道氧化物层图案中的材料，以及第一和第二导电层图案。 栅极结构包括至少覆盖第二导电层图案的侧壁的第一间隔物。 栅极结构包括覆盖第一间隔物的侧壁和第一导电层图案的侧壁的第二间隔物，并且包括具有等于或大于第一介电常数的第二介电常数的材料。 在包括栅极结构的非易失性存储器件中，由于后部隧道引起的擦除饱和度降低。