公开(公告)号：US11348930B2

公开(公告)日：2022-05-31

申请号：US16668222

申请日：2019-10-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Janggn Yun ,  Jaeduk Lee

IPC分类号： H01L27/11548 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/522

摘要： A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US20230005953A1

公开(公告)日：2023-01-05

申请号：US17728317

申请日：2022-04-25

申请人： Samsung Electronics Co., Ltd.

发明人： Youngjin Jung ,  Sora Kim ,  Haeli Park ,  Kwuiyeon Yu ,  Janggn Yun

IPC分类号： H01L27/11582 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

摘要： An integrated circuit device according to the inventive concept includes: a semiconductor substrate including a cell region and a connection region; a gate stack including a plurality of gate electrodes and a plurality of insulating layers extending on a main surface of the semiconductor substrate in a horizontal direction and alternately stacked thereon in a vertical direction, the gate stack having a stair structure in the connection region; and a plurality of contact plugs in the connection region, wherein, in a portion of the connection region, a first length, in the horizontal direction, of a first gate electrode that is located in the lowest layer among the plurality of gate electrodes is less than a second length, in the horizontal direction, of a second gate electrode that is located above the first gate electrode.

公开(公告)号：US20240324233A1

公开(公告)日：2024-09-26

申请号：US18598414

申请日：2024-03-07

申请人： Samsung Electronics Co., Ltd.

发明人： Kyeonghoon Park ,  Jaebok Baek ,  Janggn Yun ,  Jeehoon Han

IPC分类号： H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC分类号： H10B43/40 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

摘要： A non-volatile memory device includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure, where the cell array structure includes a base insulation layer, a common source line layer on the base insulation layer, a buffer insulation layer on the common source line layer, and a cell stack on the buffer insulation layer, where the cell stack includes a plurality of gate electrodes and a plurality of insulation layers, where the plurality of gate electrodes have a staircase shape, a plurality of gate contact plugs that extend into the cell stack, and a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer.

公开(公告)号：US11895837B2

公开(公告)日：2024-02-06

申请号：US17737164

申请日：2022-05-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Janggn Yun ,  Jaeduk Lee

IPC分类号： H10B41/50 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC分类号： H10B41/50 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

摘要： A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US11569262B2

公开(公告)日：2023-01-31

申请号：US17036034

申请日：2020-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Janggn Yun ,  Jaeduk Lee ,  Dongwhee Kwon

IPC分类号： H01L27/11582 ,  H01L27/24 ,  H01L23/535 ,  H01L27/11556

摘要： A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.