公开(公告)号：US20250056807A1

公开(公告)日：2025-02-13

申请号：US18790129

申请日：2024-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong Min ,  Jaebok Baek ,  Taekkyu Yoon ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, active regions extending on the substrate in a first direction, the active regions spaced apart from each other in a second direction perpendicular to the first direction, and arranged in a third direction oblique to the first direction and second direction, and gate electrodes disposed on the active regions and including a first edge extending in the second direction, a second edge extending in the first direction, and a corner region defined by the first edge and the second edge, wherein the corner region includes a protrusion having a width narrowing in a direction away from a center of each of the gate electrodes in plan view.

公开(公告)号：US20240324233A1

公开(公告)日：2024-09-26

申请号：US18598414

申请日：2024-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Jaebok Baek ,  Janggn Yun ,  Jeehoon Han

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A non-volatile memory device includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure, where the cell array structure includes a base insulation layer, a common source line layer on the base insulation layer, a buffer insulation layer on the common source line layer, and a cell stack on the buffer insulation layer, where the cell stack includes a plurality of gate electrodes and a plurality of insulation layers, where the plurality of gate electrodes have a staircase shape, a plurality of gate contact plugs that extend into the cell stack, and a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer.

公开(公告)号：US11856770B2

公开(公告)日：2023-12-26

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jaebok Baek ,  Giyong Chung ,  Jeehoon Han

IPC: H10B43/10 ,  H01L25/18 ,  H01L25/065 ,  H10B43/27 ,  H01L23/00

CPC classification number: H10B43/10 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US20230380164A1

公开(公告)日：2023-11-23

申请号：US18116434

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Inhwan Baek ,  Jaebok Baek ,  Jeehoon Han ,  Seungyoon Kim ,  Heesuk Kim ,  Byoungjae Park ,  Jongseon Ahn ,  Jumi Yun

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.