公开(公告)号：US20190096875A1

公开(公告)日：2019-03-28

申请号：US16001273

申请日：2018-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

CPC classification number: H01L27/0292 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/528 ,  H01L27/0248

Abstract: A semiconductor device can include a front-end-of-line region on a substrate, where the front-end-of-line region can include an electrostatic discharge protection circuit and an integrated circuit electrically connected to the electrostatic discharge protection circuit. A back-end-of-line region can be on the front-end-of-line region and an electrostatic discharge protection pattern can be on a scribe region of the substrate. The electrostatic discharge protection pattern can include a lower pattern extending horizontally and a side cross-sectional surface defined by a height and a width of the lower pattern, where the side cross-sectional surface can be exposed outside the back-end-of-line region. A via can be electrically connected to the lower pattern and extend perpendicularly to the substrate and an upper pattern can be electrically connected to the via.

公开(公告)号：US20240266307A1

公开(公告)日：2024-08-08

申请号：US18390205

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh ,  Wangsun Lim ,  Manhee Han ,  Jaeyoung Hong

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/03 ,  H01L21/56 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0384 ,  H01L2224/0391 ,  H01L2224/96 ,  H01L2224/97

Abstract: Provided is a method of fabricating a semiconductor package, the method including forming a passivation layer and a first protective layer covering a semiconductor substrate and conductive pad above a first surface of the semiconductor substrate, removing a portion of the passivation layer and a portion of the first protective layer to expose the conductive pad, forming a second protective layer covering the conductive pad on the first protective layer, grinding a second surface opposite the first surface of the semiconductor substrate, dicing the semiconductor substrate, and removing the second protective layer to expose the conductive pad, wherein the second protective layer does not expose the conductive pad during the grinding and during the dicing.

公开(公告)号：US12213313B2

公开(公告)日：2025-01-28

申请号：US17570828

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh

IPC: H10B41/40 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.

公开(公告)号：US11508681B2

公开(公告)日：2022-11-22

申请号：US16988136

申请日：2020-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Younhee Kang ,  Junghyun Roh

IPC: H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

公开(公告)号：US20210311104A1

公开(公告)日：2021-10-07

申请号：US17061380

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh ,  Minjae Lee ,  Unho Cha

IPC: G01R31/26 ,  H01L23/552 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US20210043592A1

公开(公告)日：2021-02-11

申请号：US16988136

申请日：2020-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Younhee Kang ,  Junghyun Roh

IPC: H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

公开(公告)号：US11796587B2

公开(公告)日：2023-10-24

申请号：US17061380

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh ,  Minjae Lee ,  Unho Cha

IPC: G01R31/26 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/522

CPC classification number: G01R31/2607 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/552

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US11217545B2

公开(公告)日：2022-01-04

申请号：US16780084

申请日：2020-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first substrate having a first surface and including a first electrode, a first bump pad located on the first surface of the first substrate and connected to the first electrode, a second substrate having a second surface facing the first surface of the first substrate and including a second electrode, a second bump pad and neighboring second bump pads on the second surface of the second substrate, and a bump structure. The second bump pad has a recess structure. That is recessed from a side surface of the second bump pad toward a center thereof. The second bump pad may be connected to the second electrode. A bump structure may contact the first bump pad and the second bump pad. The bump structure may have a portion protruding through the recess structure. The neighboring second bump pads may neighbor the second bump pad and include recess structures oriented in different directions.

公开(公告)号：US20200328168A1

公开(公告)日：2020-10-15

申请号：US16567426

申请日：2019-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh

IPC: H01L23/00

Abstract: A semiconductor chip includes a redistribution layer having an improved reliability. The semiconductor chip includes a device layer on a semiconductor substrate, a wiring structure on the device layer, a cover insulating layer on the wiring structure, and a redistribution layer. The device layer includes a semiconductor device. The wiring structure includes an internal connection pad electrically connected to the semiconductor device. The cover insulating layer includes a first recess filled with a connection via connected to the internal connection pad and a second recess having a depth that is less than that of the first recess. The redistribution layer in connected to the connection via and extends along an upper surface of the cover insulating layer.

公开(公告)号：US10510746B2

公开(公告)日：2019-12-17

申请号：US16001273

申请日：2018-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/525

Abstract: A semiconductor device can include a front-end-of-line region at least a portion of which is disposed on a substrate, where the front-end-of-line region can include an electrostatic discharge protection circuit and an integrated circuit electrically connected to the electrostatic discharge protection circuit. A back-end-of-line region can be on the front-end-of-line region and an electrostatic discharge protection pattern can be on a scribe region of the substrate. The electrostatic discharge protection pattern can include a lower pattern extending horizontally and a side cross-sectional surface defined by a height and a width of the lower pattern, where the side cross-sectional surface can be exposed through a side surface of the back-end-of-line region. A via can be electrically connected to the lower pattern and extend perpendicularly to the substrate and an upper pattern can be electrically connected to the via.