公开(公告)号：US09397052B2

公开(公告)日：2016-07-19

申请号：US14291698

申请日：2014-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Hyunsuk Chun

IPC: H01L23/49 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06135 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.

Abstract translation: 半导体封装包括封装基板，安装在封装基板上的第一半导体芯片，安装在第一半导体芯片上以暴露第一半导体芯片的至少一部分的第二半导体芯片，以及设置在边缘的应力消除结构 并且被配置为减轻施加在第一半导体芯片和第二半导体芯片之间的应力。

公开(公告)号：US12080479B2

公开(公告)日：2024-09-03

申请号：US17990120

申请日：2022-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae Park

IPC: H01G4/005 ,  H01G4/224

CPC classification number: H01G4/005 ,  H01G4/224

Abstract: A chip capacitor includes a substrate, a plurality of capacitor wires on the substrate, and a mold layer disposed on the substrate to cover the capacitor wires. Each of the capacitor wires includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

公开(公告)号：US10777495B2

公开(公告)日：2020-09-15

申请号：US16126221

申请日：2018-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/14 ,  H01L21/683 ,  H01L25/10 ,  H01L23/00

Abstract: A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.

公开(公告)号：US10134666B2

公开(公告)日：2018-11-20

申请号：US15926287

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae Park ,  Kyujin Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.

公开(公告)号：US09402315B2

公开(公告)日：2016-07-26

申请号：US14457493

申请日：2014-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsuk Chun ,  Soojae Park ,  Seungbae Lee ,  Sangsu Ha

IPC: H05K1/18 ,  H05K1/11 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H05K1/18 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81121 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a semiconductor package including a wiring substrate having top and bottom surfaces. A first semiconductor chip is disposed on the wiring substrate in a flip-chip manner. The first semiconductor chip has a first surface facing the top surface of the wiring substrate and a second surface opposite to the first surface. First connection members are disposed between the wiring substrate and the first semiconductor chip. The first connection members include first and second contact members each including one or more magnetic materials. The first contact members include portions disposed in the second contact members. The one or more magnetic material of the first contact members have an opposite polar orientation to that of the second contact members.

Abstract translation: 提供一种包括具有顶表面和底表面的布线基板的半导体封装。 第一半导体芯片以倒装芯片的方式设置在布线基板上。 第一半导体芯片具有面对布线基板的上表面的第一表面和与第一表面相对的第二表面。 第一连接构件设置在布线基板和第一半导体芯片之间。 第一连接构件包括每个包括一个或多个磁性材料的第一和第二接触构件。 第一接触构件包括设置在第二接触构件中的部分。 第一接触构件的一个或多个磁性材料具有与第二接触构件相反的极性取向。

公开(公告)号：US12267962B2

公开(公告)日：2025-04-01

申请号：US17981847

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae Park

IPC: H05K1/16 ,  H01G4/01 ,  H01G4/012 ,  H01G4/28 ,  H01G4/38 ,  H01L23/00 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H01G4/008 ,  H01G4/12 ,  H01L23/31

Abstract: A wiring board includes an insulating layer having a first surface and a second surface, which are opposite to each other, upper wiring patterns on the first surface of the insulating layer, lower wiring patterns on the second surface of the insulating layer, intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns, and a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns. The capacitor wire includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

公开(公告)号：US11508681B2

公开(公告)日：2022-11-22

申请号：US16988136

申请日：2020-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Younhee Kang ,  Junghyun Roh

IPC: H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

公开(公告)号：US20210043592A1

公开(公告)日：2021-02-11

申请号：US16988136

申请日：2020-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Younhee Kang ,  Junghyun Roh

IPC: H01L23/00

Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

公开(公告)号：US10147616B2

公开(公告)日：2018-12-04

申请号：US14922406

申请日：2015-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae Park ,  Geunwoo Kim ,  Keunho Jang ,  Younjo Mun

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L21/50 ,  H01L23/498

Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.

公开(公告)号：US09960107B2

公开(公告)日：2018-05-01

申请号：US15385062

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae Park ,  Kyujin Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05432 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.