公开(公告)号：US09929098B2

公开(公告)日：2018-03-27

申请号：US15048998

申请日：2016-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Yim ,  Sang-Hoon Ahn ,  Thomas Oszinda ,  Jong-Min Baek ,  Byung Hee Kim ,  Nae-In Lee ,  Kee-Young Jun

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53295

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

公开(公告)号：US20200071822A1

公开(公告)日：2020-03-05

申请号：US16371327

申请日：2019-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Joo An ,  Jeon-Il Lee ,  Kaoru Yamamoto ,  Jang-Hee Lee ,  Kee-Young Jun ,  Geun-O Jeong

IPC: C23C16/455 ,  H01L21/67 ,  H01J37/32 ,  C23C16/50 ,  C23C16/46

Abstract: A semiconductor manufacturing, apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is co figured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.

公开(公告)号：US11270881B2

公开(公告)日：2022-03-08

申请号：US16385441

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kaoru Yamamoto ,  Chang-Hyun Kim ,  Hyun-Jae Song ,  Keun-Wook Shin ,  Hyeon-Jin Shin ,  Sung-Joo An ,  Chang-Seok Lee ,  Kee-Young Jun ,  Geun-O Jeong ,  Jang-Hee Lee

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67

Abstract: In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.

公开(公告)号：US11508557B2

公开(公告)日：2022-11-22

申请号：US16371327

申请日：2019-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Joo An ,  Jeon-Il Lee ,  Kaoru Yamamoto ,  Jang-Hee Lee ,  Kee-Young Jun ,  Geun-O Jeong

IPC: C23C16/00 ,  H01L21/306 ,  H01J37/32 ,  H01L21/67 ,  C23C16/50 ,  C23C16/46

Abstract: A semiconductor manufacturing apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is configured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.

公开(公告)号：US09653400B2

公开(公告)日：2017-05-16

申请号：US14984085

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Yim ,  Woo-Kyung You ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Thomas Oszinda ,  Kee-Young Jun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.