公开(公告)号：US10361319B2

公开(公告)日：2019-07-23

申请号：US15981578

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

公开(公告)号：US09953883B2

公开(公告)日：2018-04-24

申请号：US15415012

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US10714397B2

公开(公告)日：2020-07-14

申请号：US16541416

申请日：2019-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/161 ,  H01L29/417 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US10461187B2

公开(公告)日：2019-10-29

申请号：US16003959

申请日：2018-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/207 ,  H01L21/306 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.

公开(公告)号：US09978881B2

公开(公告)日：2018-05-22

申请号：US15598675

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

公开(公告)号：US10453756B2

公开(公告)日：2019-10-22

申请号：US15937037

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L29/417

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US20180294353A1

公开(公告)日：2018-10-11

申请号：US16003959

申请日：2018-06-08

Applicant: Samsung Electronics Co., Ltd

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L29/78 ,  H01L29/207 ,  H01L29/66 ,  H01L29/423 ,  H01L21/306 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/7827 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66666

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other

公开(公告)号：US10020396B2

公开(公告)日：2018-07-10

申请号：US15350686

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon-cheol Heo ,  Maria Toledano Luque

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/207 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66666

Abstract: An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first direction perpendicular to the main surface and including a first section and a second section alternately arranged in the first direction, a gate electrode covering the first section, and a gate dielectric layer between the first section and the gate electrode. The first section and the second section may have the same composition as each other and may have different crystal phases from each other.