公开(公告)号：US20240339411A1

公开(公告)日：2024-10-10

申请号：US18395839

申请日：2023-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHENGTAR WU ,  JONGKOOK KIM ,  SEUNGYEON RHEE ,  CHOONGBIN YIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.