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公开(公告)号：US20190096869A1
公开(公告)日：2019-03-28
申请号：US16201021
申请日：2018-11-27
发明人： Young Lyong KIM , Jin-woo PARK , CHOONGBIN YIM , Younji MIN
IPC分类号： H01L25/00 , H01L25/10 , H01L23/538 , H01L23/31 , H01L23/29 , H01L23/00 , H01L21/56 , H01L25/065
摘要： Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.
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公开(公告)号：US20140374883A1
公开(公告)日：2014-12-25
申请号：US14197203
申请日：2014-03-04
发明人： CHOONGBIN YIM , HYEONGMUN KANG , TAESUNG PARK , EUNCHUL AHN
IPC分类号： H01L23/544 , H01L21/3105
CPC分类号： H01L23/544 , H01L21/3105 , H01L23/3114 , H01L23/3128 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.
摘要翻译： 一种半导体封装，包括：半导体衬底; 半导体衬底上的模具层; 以及形成在所述模具层的表面上的标记，所述标记包括基本上不连续地布置在显示区域的垂直和水平方向上的点标记。 标记的单位显示区域内的点标记的有效面积小于单位显示区域的总面积的约一半。
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公开(公告)号：US20240290762A1
公开(公告)日：2024-08-29
申请号：US18519211
申请日：2023-11-27
发明人： CHOONGBIN YIM , JONGKOOK KIM
IPC分类号： H01L25/10 , H01L23/31 , H01L23/538 , H01L25/065 , H10B80/00
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H10B80/00 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/08235 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
摘要： A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate, wherein the connection substrate includes an opening extending through the connection substrate, a chip structure including a first semiconductor chip in the opening and on the first redistribution substrate, a first interposer substrate including a through electrode extending through the first interposer substrate in the opening and on the first redistribution substrate, wherein the first interposer substrate is spaced apart from the chip structure, a second semiconductor chip on the first interposer substrate and electrically connected to the through electrode, a first molding layer on the chip structure, first interposer substrate, and second semiconductor chip, and a second redistribution substrate on the first molding layer and connection substrate, wherein a lower surface of the chip structure and the first interposer substrate are in electrical contact with an upper surface of the first redistribution substrate.
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公开(公告)号：US20210407923A1
公开(公告)日：2021-12-30
申请号：US17167789
申请日：2021-02-04
发明人： DONGHO KIM , JONGBO SHIM , HWAN PIL PARK , CHOONGBIN YIM , JUNGWOO KIM
IPC分类号： H01L23/538 , H01L23/13 , H01L23/31 , H01L23/00 , H01L25/065 , H01L25/10
摘要： A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.
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公开(公告)号：US20240339411A1
公开(公告)日：2024-10-10
申请号：US18395839
申请日：2023-12-26
发明人： CHENGTAR WU , JONGKOOK KIM , SEUNGYEON RHEE , CHOONGBIN YIM
CPC分类号： H01L23/5385 , H01L21/486 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/05 , H01L24/08 , H01L2224/05647 , H01L2224/08225 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
摘要： A semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.
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公开(公告)号：US20230402358A1
公开(公告)日：2023-12-14
申请号：US18174992
申请日：2023-02-27
发明人： CHOONGBIN YIM , JI-YONG PARK , JIN-WOO PARK
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49816 , H01L23/3107 , H01L24/24 , H01L2224/24225 , H01L2224/19 , H01L24/19 , H01L2224/24011 , H01L25/18
摘要： A semiconductor package includes a package substrate, substrate pads provided on a top surface of the package substrate, at least one core ball on at least one of the substrate pads, a redistribution substrate provided on the top surface of the package substrate, and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate is electrically connected to the package substrate through a plurality of solder balls provided on a bottom surface of the redistribution substrate. The at least one core ball is electrically connected to the redistribution substrate. A diameter of the at least one core ball is greater than a diameter of each of the plurality of solder balls.
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