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公开(公告)号：US20240339411A1
公开(公告)日：2024-10-10
申请号：US18395839
申请日：2023-12-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： CHENGTAR WU , JONGKOOK KIM , SEUNGYEON RHEE , CHOONGBIN YIM
CPC classification number: H01L23/5385 , H01L21/486 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/05 , H01L24/08 , H01L2224/05647 , H01L2224/08225 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.
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公开(公告)号：US20190164851A1
公开(公告)日：2019-05-30
申请号：US16047439
申请日：2018-07-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JONGWOON YOO , DAEHA HWANG , YOUNG-GI MIN , SOOYONG PARK , JONGKOOK KIM
Abstract: A test system includes automatic test equipment configured to test a device under test, and a test interface board configured to measure a second voltage applied to the device under test based on a first voltage supplied from the automatic test equipment. The test interface board includes a sensing wiring configured to transmit the measured second voltage to the automatic test equipment. The second voltage is measured at an interior location of the device under test.
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Patent Agency Ranking
公开(公告)号：US20150155216A1
公开(公告)日：2015-06-04
申请号：US14491957
申请日：2014-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： JONGKOOK KIM , BYOUNG WOOK JANG
IPC: H01L23/31 , H01L21/02 , H01L21/3105 , H01L23/00
CPC classification number: H01L23/3171 , H01L23/3114 , H01L23/3157 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/05573 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/06132 , H01L2224/13014 , H01L2224/13022 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/07025 , H01L2924/14 , H01L2924/351 , H01L2924/00014
Abstract: A semiconductor chip comprising: a substrate; a plurality of pads disposed on the substrate; and a plurality of passivation patterns laterally separated from each other on the substrate, each of the passivation patterns including a plurality of openings, the openings exposing at least one pad of the pads, and the passivation patterns having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate.
Abstract translation: 一种半导体芯片，包括：基板; 设置在所述基板上的多个焊盘; 以及在衬底上彼此横向分离的多个钝化图案，每个钝化图案包括多个开口，所述开口暴露至少一个衬垫垫，并且所述钝化图案具有不同于热的热膨胀系数 底物的膨胀系数。
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公开(公告)号：US20250062260A1
公开(公告)日：2025-02-20
申请号：US18608838
申请日：2024-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD,
Inventor： CHOONGBIN YIM , JONGKOOK KIM , Chengtar Wu
Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a second semiconductor chip disposed on the first semiconductor chip; a passive component disposed on the first semiconductor chip; and an encapsulant that encapsulates the second semiconductor chip and the passive component. The first semiconductor chip includes a first through via that extends through at least a portion of the first semiconductor chip, and a first pad disposed on a first surface thereof and connected to the first through via. The passive component includes at least one trench and a second pad disposed on a first surface thereof and connected to the trench. The first pad and the second pad are directly bonded by contacting each other.
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公开(公告)号：US20240290762A1
公开(公告)日：2024-08-29
申请号：US18519211
申请日：2023-11-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： CHOONGBIN YIM , JONGKOOK KIM
IPC: H01L25/10 , H01L23/31 , H01L23/538 , H01L25/065 , H10B80/00
CPC classification number: H01L25/105 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H10B80/00 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/08235 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate, wherein the connection substrate includes an opening extending through the connection substrate, a chip structure including a first semiconductor chip in the opening and on the first redistribution substrate, a first interposer substrate including a through electrode extending through the first interposer substrate in the opening and on the first redistribution substrate, wherein the first interposer substrate is spaced apart from the chip structure, a second semiconductor chip on the first interposer substrate and electrically connected to the through electrode, a first molding layer on the chip structure, first interposer substrate, and second semiconductor chip, and a second redistribution substrate on the first molding layer and connection substrate, wherein a lower surface of the chip structure and the first interposer substrate are in electrical contact with an upper surface of the first redistribution substrate.
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公开(公告)号：US20250022844A1
公开(公告)日：2025-01-16
申请号：US18444359
申请日：2024-02-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： CHOONGBIN YIM , JONGKOOK KIM
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/528 , H01L25/00 , H01L25/18
Abstract: A semiconductor package according to an embodiment may include, a redistribution layer structure; a first semiconductor stack structure on an upper surface of the redistribution layer structure, wherein the first semiconductor stack structure includes a first chiplet and a second chiplet disposed on the first chiplet; a second semiconductor stack structure on an upper surface of the redistribution layer structure side by side with the first semiconductor stack structure; a bridge die forming an electrical connection between the first semiconductor stack structure and the second semiconductor stack structure, the bridge die being disposed above the first semiconductor stack structure and the second semiconductor stack structure; and a surface mount device (SMD) disposed on an upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure.
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公开(公告)号：US20240395720A1
公开(公告)日：2024-11-28
申请号：US18395821
申请日：2023-12-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： CHOONGBIN YIM , JONGKOOK KIM
IPC: H01L23/538 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L25/00 , H01L25/065 , H01L25/10 , H10B80/00
Abstract: A semiconductor package includes: a first redistribution layer structure; a first semiconductor die disposed on the first redistribution layer structure; a second semiconductor die disposed adjacent to the first semiconductor die on the first redistribution layer structure; a molding material positioned on the first redistribution layer structure, and covering the first semiconductor die and the second semiconductor die; a bridge die positioned on the molding material, the first semiconductor die, and the second semiconductor die, and electrically connecting the first semiconductor die and the second semiconductor die to each other; a substrate positioned on the molding material, the first semiconductor die, and the second semiconductor die, and at least partially surrounding the bridge die; and a second redistribution layer structure disposed on the bridge die and the substrate.
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