公开(公告)号：US20200303413A1

公开(公告)日：2020-09-24

申请号：US16892384

申请日：2020-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun SHIN ,  Hyun Mog PARK ,  Joong Shik SHIN

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/788 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20240315030A1

公开(公告)日：2024-09-19

申请号：US18675030

申请日：2024-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jun SHIN ,  Hyun Mog PARK ,  Joong Shik SHIN

IPC: H10B43/27 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/41775 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20210366928A1

公开(公告)日：2021-11-25

申请号：US17394499

申请日：2021-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun SHIN ,  Hyun Mog PARK ,  Joong Shik SHIN

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/788 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20240414358A1

公开(公告)日：2024-12-12

申请号：US18679066

申请日：2024-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun SHIN ,  Su Ji KIM ,  Young Hun SUNG

IPC: H04N19/186 ,  H04N19/103 ,  H04N19/119 ,  H04N19/177 ,  H04N19/42

Abstract: An apparatus for implicit neural video representation is provided. The apparatus for implicit neural video representation includes: a first neural network configured to output pixel-to-pixel matching information up to a keyframe by using space-time coordinates of a video as input; and a second neural network configured to output Red-Green-Blue (RGB) data by using the space-time coordinates and the output pixel-to-pixel matching information as input.

公开(公告)号：US20190027490A1

公开(公告)日：2019-01-24

申请号：US15933544

申请日：2018-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun SHIN ,  Hyun Mog PARK ,  Joong Shik SHIN

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L27/11582 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/41775 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.