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    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230112006A1

    公开(公告)日：2023-04-13

    申请号：US17826521

    申请日：2022-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230070532A1

    公开(公告)日：2023-03-09

    申请号：US17726363

    申请日：2022-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

    IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

    SEMICONDUCTOR PACKAGE COMPRISING ADHESION ENHANCER LAYER AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR PACKAGE COMPRISING ADHESION ENHANCER LAYER AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250022764A1

    公开(公告)日：2025-01-16

    申请号：US18412770

    申请日：2024-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung KIM ,  Solji SONG ,  Jiseok YEO ,  Hyojun YOON ,  Dongjin LEE ,  Yoonseok CHOI

    IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate including bonding pads on a upper surface thereof and external connectors on a lower surface thereof, a first chip structure connected to the package substrate with a bonding wire and disposed on the package substrate, a second chip structure disposed on the package substrate and disposed next to the first chip structure, and a mold layer covering the package substrate, the first chip structure, and the second chip structure, wherein the first chip structure includes a plurality of semiconductor dies that are sequentially stacked, the second chip structure includes a second semiconductor substrate, an oxide layer on the second semiconductor substrate, and an adhesion enhancer layer disposed on the oxide layer and in contact with the mold layer, heights of the first chip structure and the second chip structure are the same.

    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE
    5.
    发明申请
    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230073690A1

    公开(公告)日：2023-03-09

    申请号：US17711370

    申请日：2022-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

    Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220077040A1

    公开(公告)日：2022-03-10

    申请号：US17318227

    申请日：2021-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi JIN ,  Gyuho KANG ,  Solji SONG ,  Un-Byoung KANG ,  Ju-Il CHOI

    IPC: H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

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