公开(公告)号：US20220068852A1

公开(公告)日：2022-03-03

申请号：US17501133

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L23/31

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20230282582A1

公开(公告)日：2023-09-07

申请号：US18196077

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Seong-Hoon BAE ,  Dongjoon OH ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US20230260923A1

公开(公告)日：2023-08-17

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L23/5383 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20220399316A1

公开(公告)日：2022-12-15

申请号：US17677453

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Sechul PARK ,  Jongho PARK ,  Junyoung PARK

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US20230238316A1

公开(公告)日：2023-07-27

申请号：US18189834

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Teahwa JEONG ,  Jeonggi JIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0652

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

公开(公告)号：US20220037261A1

公开(公告)日：2022-02-03

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20220020714A1

公开(公告)日：2022-01-20

申请号：US17204313

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Junyoung PARK ,  Seong-Hoon BAE ,  Jin Ho AN

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

公开(公告)号：US20200098711A1

公开(公告)日：2020-03-26

申请号：US16404841

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L25/16

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20250015009A1

公开(公告)日：2025-01-09

申请号：US18885904

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20240429214A1

公开(公告)日：2024-12-26

申请号：US18820569

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Sechul PARK ,  Jongho PARK ,  Junyoung PARK

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.