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    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    2.
    发明申请
    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220059442A1

    公开(公告)日：2022-02-24

    申请号：US17230511

    申请日：2021-04-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

    IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538

    摘要： Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE
    7.
    发明申请
    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230073690A1

    公开(公告)日：2023-03-09

    申请号：US17711370

    申请日：2022-04-01

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

    IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/544

    摘要： A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210398913A1

    公开(公告)日：2021-12-23

    申请号：US17466750

    申请日：2021-09-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Dongjoon OH ,  Sukho LEE ,  Jusuk KANG

    IPC分类号： H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

    摘要： A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.

    SEMICONDUCTOR PACKAGES
    9.
    发明公开
    SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20240312894A1

    公开(公告)日：2024-09-19

    申请号：US18668974

    申请日：2024-05-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

    IPC分类号： H01L23/498

    CPC分类号： H01L23/49838 ,  H01L23/49822

    摘要： A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230112006A1

    公开(公告)日：2023-04-13

    申请号：US17826521

    申请日：2022-05-27

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

    IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/48

    摘要： A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.