公开(公告)号：US20220037261A1

公开(公告)日：2022-02-03

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20230282582A1

公开(公告)日：2023-09-07

申请号：US18196077

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Seong-Hoon BAE ,  Dongjoon OH ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US20220059442A1

公开(公告)日：2022-02-24

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20240290702A1

公开(公告)日：2024-08-29

申请号：US18655879

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20230073690A1

公开(公告)日：2023-03-09

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US20230112006A1

公开(公告)日：2023-04-13

申请号：US17826521

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20220068779A1

公开(公告)日：2022-03-03

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Jeonggi JIN ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20250015009A1

公开(公告)日：2025-01-09

申请号：US18885904

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20240128239A1

公开(公告)日：2024-04-18

申请号：US18471875

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Junyun KWEON ,  Byeongchan KIM ,  Jumyong PARK ,  Dongjoon OH ,  Hyunchul JUNG ,  Hyunsu HWANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor package includes a connection structure, a via protection layer on the connection structure, a first semiconductor chip on the via protection layer and including a first substrate having a first active face and a first inactive face opposite to each other a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure, and a second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip. The second semiconductor chip includes a second substrate having a second active face and a second inactive face opposite to each other. The package includes a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other, and a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer encloses the conductive post.

公开(公告)号：US20210384137A1

公开(公告)日：2021-12-09

申请号：US17147661

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-IL CHOI ,  Gyuho KANG ,  Seong-Hoon BAE ,  Dongjoon OH ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.