公开(公告)号：US11443785B2

公开(公告)日：2022-09-13

申请号：US17344610

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sucheol Lee ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/17736 ,  H03K19/017 ,  H03K19/1776

Abstract: A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.

公开(公告)号：US20220238146A1

公开(公告)日：2022-07-28

申请号：US17483010

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk Woo ,  Changkyu Seol ,  Cheolmin Park ,  Sucheol Lee ,  Chanik Park

IPC: G11C7/22 ,  G11C7/16 ,  H01L25/065

Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

公开(公告)号：US11501805B2

公开(公告)日：2022-11-15

申请号：US17377654

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sucheol Lee ,  Changkyu Seol ,  Byungsuk Woo

IPC: G11C5/14 ,  G11C11/4074

Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

公开(公告)号：US20220076715A1

公开(公告)日：2022-03-10

申请号：US17347998

申请日：2021-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sucheol Lee ,  Younghoon Son ,  Hyunyoon Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/10 ,  H03K19/017 ,  H03K7/02

Abstract: A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.

公开(公告)号：US12100469B2

公开(公告)日：2024-09-24

申请号：US17962992

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsuk Woo ,  Sucheol Lee ,  Changkyu Seol

IPC: G11C7/10 ,  G11C7/04 ,  G11C7/14

CPC classification number: G11C7/1063 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/14

Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

公开(公告)号：US11574662B2

公开(公告)日：2023-02-07

申请号：US17347998

申请日：2021-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sucheol Lee ,  Younghoon Son ,  Hyunyoon Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/10 ,  G06F13/16 ,  H03K7/02 ,  H03K19/017

Abstract: A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.

公开(公告)号：US11757567B2

公开(公告)日：2023-09-12

申请号：US17590474

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Jiyoup Kim ,  Hyejeong So ,  Myoungbo Kwak ,  Pilsang Yoon ,  Sucheol Lee ,  Jinsoo Lim ,  Youngdon Choi

IPC: H04L1/00 ,  G06F1/03

CPC classification number: H04L1/0041 ,  G06F1/03 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0084

Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

公开(公告)号：US11631444B2

公开(公告)日：2023-04-18

申请号：US17483010

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk Woo ,  Changkyu Seol ,  Cheolmin Park ,  Sucheol Lee ,  Chanik Park

IPC: G11C7/22 ,  H01L25/065 ,  G11C7/16 ,  H01L27/108

Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

公开(公告)号：US11449274B2

公开(公告)日：2022-09-20

申请号：US17356687

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsuk Woo ,  Changkyu Seol ,  Sucheol Lee

IPC: G06F3/06

Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

公开(公告)号：US20220215865A1

公开(公告)日：2022-07-07

申请号：US17463635

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsuk Woo ,  Sucheol Lee ,  Changkyu Seol

IPC: G11C7/10 ,  G11C7/04 ,  G11C7/14

Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.