公开(公告)号：US12040402B2

公开(公告)日：2024-07-16

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US12027596B2

公开(公告)日：2024-07-02

申请号：US18201308

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US11569389B2

公开(公告)日：2023-01-31

申请号：US17470341

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Seung Mo Kang ,  Yong Seung Kim ,  Jung Taek Kim ,  Min-Hee Choi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

公开(公告)号：US20230253449A1

公开(公告)日：2023-08-10

申请号：US17935528

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk Shin ,  Hyun-Kwan Yu ,  Seok Hoon Kim ,  Pan Kwi Park ,  Yong Seung Kim ,  Jung Taek Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4232 ,  H01L29/66553

Abstract: A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

公开(公告)号：US11688778B2

公开(公告)日：2023-06-27

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20230145260A1

公开(公告)日：2023-05-11

申请号：US17831513

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including: a plurality of fin-shaped patterns spaced apart from each other in a first direction and extending in a second direction on a substrate; a field insulating layer covering sidewalls of the plurality of fin-shaped patterns and disposed between the fin-shaped patterns; a source/drain pattern connected to the plurality of fin-shaped patterns on the field insulating layer, the source/drain pattern including bottom surfaces respectively connected to the fin-shaped patterns, and at least one connection surface connecting the bottom surfaces to each other; and a sealing insulating pattern extending along the connection surface of the source/drain pattern and an upper surface of the field insulating layer, wherein the source/drain pattern includes a silicon-germanium pattern doped with a p-type impurity.

公开(公告)号：US11133421B2

公开(公告)日：2021-09-28

申请号：US16808857

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Seung Mo Kang ,  Yong Seung Kim ,  Jung Taek Kim ,  Min-Hee Choi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.