公开(公告)号：US20170309339A1

公开(公告)日：2017-10-26

申请号：US15439858

申请日：2017-02-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chia-Lin Hsiung ,  Yanbin An ,  Alexander Chu ,  Fumiaki Toyama

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11573 ,  H01L27/11582

Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.

公开(公告)号：US10726921B2

公开(公告)日：2020-07-28

申请号：US15942044

申请日：2018-03-30

Applicant: SanDisk Technologies LLC

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C11/34 ,  G11C16/08 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

公开(公告)号：US20190088335A1

公开(公告)日：2019-03-21

申请号：US15942044

申请日：2018-03-30

Applicant: SanDisk Technologies LLC

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C16/08 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  G11C16/04

Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

公开(公告)号：US09922716B2

公开(公告)日：2018-03-20

申请号：US15439858

申请日：2017-02-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chia-Lin Hsiung ,  Yanbin An ,  Alexander Chu ,  Fumiaki Toyama

IPC: G11C16/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11573 ,  H01L27/11582

Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.