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公开(公告)号：US10249640B2
公开(公告)日：2019-04-02
申请号：US15176674
申请日：2016-06-08
发明人： Jixin Yu , Zhenyu Lu , Alexander Chu , Kensuke Yamaguchi , Hiroyuki Ogawa , Daxin Mao , Yan LI , Johann Alsmeier
IPC分类号： H01L27/11582 , H01L27/11573 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.
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公开(公告)号：US10115440B2
公开(公告)日：2018-10-30
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US20180197586A1
公开(公告)日：2018-07-12
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
CPC分类号： G11C8/08 , G06F13/4072 , G11C5/06 , G11C8/10 , G11C8/14 , G11C16/08 , H01L27/112 , H01L27/11575 , H01L27/11582
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US10256248B2
公开(公告)日：2019-04-09
申请号：US15175450
申请日：2016-06-07
发明人： Zhenyu Lu , Jixin Yu , Johann Alsmeier , Fumiaki Toyama , Yuki Mizutani , Hiroyuki Ogawa , Chun Ge , Daxin Mao , Yanli Zhang , Alexander Chu , Yan Li
IPC分类号： H01L27/11582 , H01L21/48 , H01L23/498 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.
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公开(公告)号：US09922716B2
公开(公告)日：2018-03-20
申请号：US15439858
申请日：2017-02-22
发明人： Chia-Lin Hsiung , Yanbin An , Alexander Chu , Fumiaki Toyama
CPC分类号： G11C16/26 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459 , H01L27/11573 , H01L27/11582
摘要： Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.
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公开(公告)号：US20170309339A1
公开(公告)日：2017-10-26
申请号：US15439858
申请日：2017-02-22
发明人： Chia-Lin Hsiung , Yanbin An , Alexander Chu , Fumiaki Toyama
CPC分类号： G11C16/26 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459 , H01L27/11573 , H01L27/11582
摘要： Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.
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