公开(公告)号：US11024387B2

公开(公告)日：2021-06-01

申请号：US17102712

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56 ,  G11C16/26

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US20200335168A1

公开(公告)日：2020-10-22

申请号：US16922037

申请日：2020-07-07

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/14 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US20200243141A1

公开(公告)日：2020-07-30

申请号：US16847377

申请日：2020-04-13

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US10541035B1

公开(公告)日：2020-01-21

申请号：US16022373

申请日：2018-06-28

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Han-Ping Chen ,  Chung-Yao Pai ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.

公开(公告)号：US10446244B1

公开(公告)日：2019-10-15

申请号：US15948761

申请日：2018-04-09

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C11/56

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

公开(公告)号：US20190259462A1

公开(公告)日：2019-08-22

申请号：US15900093

申请日：2018-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.

公开(公告)号：US20190074062A1

公开(公告)日：2019-03-07

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

公开(公告)号：US10115464B1

公开(公告)日：2018-10-30

申请号：US15699490

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/12 ,  G11C16/24 ,  G11C16/28 ,  G11C16/34

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a dummy memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the dummy memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the dummy memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US11244734B2

公开(公告)日：2022-02-08

申请号：US16728716

申请日：2019-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Henry Chin ,  Ching-Huang Lu

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  G11C16/26

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.

公开(公告)号：US11195857B2

公开(公告)日：2021-12-07

申请号：US16816691

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Ching-Huang Lu ,  Murshed Chowdhury ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11519

Abstract: A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.