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公开(公告)号：US11972810B2
公开(公告)日：2024-04-30
申请号：US17845430
申请日：2022-06-21
发明人： Han-Ping Chen , Wei Zhao , Henry Chin
CPC分类号： G11C16/3436 , G11C16/08 , G11C16/102 , G11C16/26
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.
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公开(公告)号：US11854620B2
公开(公告)日：2023-12-26
申请号：US17351533
申请日：2021-06-18
发明人： Erika Penzo , Han-Ping Chen , Henry Chin
CPC分类号： G11C16/08 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459 , H10B41/27 , H10B43/27
摘要： An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
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3.发明公开公开(公告)号：US20230410920A1
公开(公告)日：2023-12-21
申请号：US17845430
申请日：2022-06-21
发明人： Han-Ping Chen , Wei Zhao , Henry Chin
CPC分类号： G11C16/3436 , G11C16/102 , G11C16/26 , G11C16/08
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.
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公开(公告)号：US10957394B1
公开(公告)日：2021-03-23
申请号：US16785973
申请日：2020-02-10
发明人： Han-Ping Chen , Wei Zhao , Henry Chin
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08 , H01L27/11582 , H01L27/1157 , G11C16/34
摘要： Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.
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公开(公告)号：US20220392551A1
公开(公告)日：2022-12-08
申请号：US17336936
申请日：2021-06-02
发明人： Hua-Ling Hsu , Henry Chin , Han-Ping Chen , Erika Penzo , Fanglin Zhang
摘要： Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
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公开(公告)号：US11521691B1
公开(公告)日：2022-12-06
申请号：US17336936
申请日：2021-06-02
发明人： Hua-Ling Hsu , Henry Chin , Han-Ping Chen , Erika Penzo , Fanglin Zhang
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10 , G11C16/24 , G11C11/56 , H01L27/11565 , G11C16/26 , H01L27/11582
摘要： Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
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公开(公告)号：US12046289B2
公开(公告)日：2024-07-23
申请号：US17940498
申请日：2022-09-08
发明人： Han-Ping Chen , Guirong Liang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/3459
摘要： A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.
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公开(公告)号：US20240079063A1
公开(公告)日：2024-03-07
申请号：US17939160
申请日：2022-09-07
发明人： Han-Ping Chen , Yanjie Wang
CPC分类号： G11C16/10 , G11C16/0483
摘要： The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.
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公开(公告)号：US20220406380A1
公开(公告)日：2022-12-22
申请号：US17351533
申请日：2021-06-18
发明人： Erika Penzo , Han-Ping Chen , Henry Chin
摘要： An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
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公开(公告)号：US11139031B1
公开(公告)日：2021-10-05
申请号：US16903886
申请日：2020-06-17
发明人： Han-Ping Chen , Guirong Liang , Henry Chin
摘要： A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to determine data states for a first set of memory cells of a neighboring word line of the set of word lines, determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell for each memory cell of the second set of memory cells, and perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells.
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