公开(公告)号：US20200373355A1

公开(公告)日：2020-11-26

申请号：US16903654

申请日：2020-06-17

Applicant: Sandisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta ,  Christopher Petti

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/22 ,  G11C11/16 ,  H01L45/00 ,  H01L43/12 ,  H01L43/02

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：US10026782B2

公开(公告)日：2018-07-17

申请号：US15633054

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoichiro Tanaka ,  Yangyin Chen ,  Chu-Chen Fu ,  Christopher Petti

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

公开(公告)号：US20190123276A1

公开(公告)日：2019-04-25

申请号：US15793247

申请日：2017-10-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal Ratnam ,  Tanmay Kumar ,  Christopher Petti

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0009 ,  H01L27/2472 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.

公开(公告)号：US10032908B1

公开(公告)日：2018-07-24

申请号：US15400244

申请日：2017-01-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Juan Saenz ,  Guangle Zhou ,  Abhijit Bandyopadhyay ,  Tanmay Kumar

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/423 ,  H01L23/528 ,  H01L29/66

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

公开(公告)号：US20170236873A1

公开(公告)日：2017-08-17

申请号：US15432544

申请日：2017-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yangyin Chen ,  Christopher Petti

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1214 ,  H01L27/2427 ,  H01L27/2481 ,  H01L29/78642 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1683

Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.

公开(公告)号：US10756186B2

公开(公告)日：2020-08-25

申请号：US15951916

申请日：2018-04-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yangyin Chen ,  Christopher Petti

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/161 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory film is formed within each memory openings. A silicon-germanium alloy layer including germanium at an atomic concentration less than 25% is deposited within each memory opening. An oxidation process is performed on the silicon-germanium alloy layer. A vertical semiconductor channel including an unoxidized remaining material portion of the silicon-germanium alloy layer is formed, which includes germanium at an atomic concentration greater than 50%.

公开(公告)号：US10534840B1

公开(公告)日：2020-01-14

申请号：US16058146

申请日：2018-08-08

Applicant: SanDisk Technologies LLC

Inventor： Christopher Petti

IPC: G11C11/22 ,  G06F17/16 ,  G11C7/12 ,  G11C7/06 ,  G06N3/04 ,  G11C13/00

Abstract: Technology is described herein for performing multiplication using non-volatile memory cells. A multiplicand may be stored a node that includes multiple non-volatile memory cells. A multiplicand is stored a node that includes multiple non-volatile memory cells. Each memory cell in the node is connected to the same bit line, in one aspect. A multiply voltage may be applied to each memory cell in the node. Each memory cell in the node responds to the multiply voltage by passing a memory cell current to a bit line. The multiply voltage(s) are simultaneously applied to each memory cell in the node, such that the memory cell current of each memory cell flows in the bit line. The magnitude of the bit line current represents a product of the multiplier and the multiplicand. Vector/vector multiplication may be performed using “n” nodes of memory cells connected to the same bit line.

公开(公告)号：US20180182771A1

公开(公告)日：2018-06-28

申请号：US15445579

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying Costa ,  Daxin Mao ,  Christopher Petti ,  Dana Lee ,  Yao-Sheng Lee

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

公开(公告)号：US10853244B2

公开(公告)日：2020-12-01

申请号：US15604994

申请日：2017-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Christopher Petti ,  Srikanth Ranganathan

IPC: G06F12/06 ,  G11C13/00 ,  C12N15/11

Abstract: A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.

公开(公告)号：US10580976B2

公开(公告)日：2020-03-03

申请号：US15924944

申请日：2018-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Takahashi ,  Vincent Shih ,  Christopher Petti

IPC: H01L45/00

Abstract: A phase change memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of memory pillar structures overlying top surfaces of the first conductive rails, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of memory pillar structures. Each memory pillar structure includes a vertical stack of structural elements including, from one end to another, a selector-side conductive element, a selector element, a selector-memory conductive element, a phase change memory element, and a memory-side conductive element. At least one structural element within the vertical stack is a laterally constricted structural element having laterally recessed sidewalls relative to sidewalls of a respective immediately vertically underlying structural element.