公开(公告)号：US20240196610A1

公开(公告)日：2024-06-13

申请号：US18350595

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryoichi EHARA ,  Kenji SUGIURA ,  Katsufumi OKAMOTO ,  Yudai TANAKA ,  Kota FUNAYAMA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A memory device is formed by forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming an access trench through a portion of the alternating stack forming an access trench fill structure in the access cavity, and iteratively performing multiple instances of a unit processing sequence. Each instance of the unit processing sequence includes a vertical recess etch step that vertically recesses the access trench fill structure and an isotropic etch step that isotropically recesses the sacrificial material layers. A finned access cavity is formed after the multiple instances of the unit processing sequence. A finned dielectric support structure is formed in the finned access cavity, and the sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20200235123A1

公开(公告)日：2020-07-23

申请号：US16816552

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenji SUGIURA ,  Mitsuteru MUSHIGA ,  Yuji FUKANO ,  Akio NISHIDA

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11568 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/105 ,  H01L23/522

Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

公开(公告)号：US20200219896A1

公开(公告)日：2020-07-09

申请号：US16241221

申请日：2019-01-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Akio NISHIDA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/768

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

公开(公告)号：US20200219895A1

公开(公告)日：2020-07-09

申请号：US16241171

申请日：2019-01-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Akio NISHIDA ,  Ryosuke KANEKO ,  Michiaki SANO

IPC: H01L27/11582 ,  H01L21/8234

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

公开(公告)号：US20190252396A1

公开(公告)日：2019-08-15

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Hisakazu OTOI ,  Shigehisa INOUE ,  Yuki FUKUDA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/762

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/40114 ,  H01L29/40117

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.