公开(公告)号：US20180033794A1

公开(公告)日：2018-02-01

申请号：US15221269

申请日：2016-07-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Raghuveer Makala ,  Yingda Dong

IPC: H01L27/115 ,  H01L27/105

CPC classification number: H01L27/1157 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

公开(公告)号：US12124247B2

公开(公告)日：2024-10-22

申请号：US17465305

申请日：2021-09-02

Applicant: SanDisk Technologies LLC

Inventor： Fei Zhou ,  Cheng-Chung Chu ,  Raghuveer Makala

IPC: G05B19/418 ,  G05B13/02 ,  H01L21/66

CPC classification number: G05B19/41875 ,  G05B13/027 ,  H01L22/20 ,  G05B2219/32335 ,  G05B2219/32368 ,  G05B2219/45031

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US10741572B2

公开(公告)日：2020-08-11

申请号：US15624006

申请日：2017-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer Makala ,  Yanli Zhang ,  Yao-Sheng Lee

IPC: H01L27/30 ,  H01L27/148 ,  H01L51/44 ,  H01L51/42 ,  H04N5/372 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/532 ,  H01L27/11573 ,  H01L23/522 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/49 ,  H01L21/768

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.

公开(公告)号：US20210397170A1

公开(公告)日：2021-12-23

申请号：US17465305

申请日：2021-09-02

Applicant: SanDisk Technologies LLC

Inventor： Fei Zhou ,  Cheng-Chung Chu ,  Raghuveer Makala

IPC: G05B19/418 ,  G05B13/02 ,  H01L21/66

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US20180122814A1

公开(公告)日：2018-05-03

申请号：US15846620

申请日：2017-12-19

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Raghuveer Makala ,  Yingda Dong

IPC: H01L27/1157 ,  H01L27/105 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

公开(公告)号：US09960180B1

公开(公告)日：2018-05-01

申请号：US15470453

申请日：2017-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer Makala ,  Rahul Sharangpani ,  Keerti Shukla ,  Yanli Zhang ,  Peng Zhang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L29/423 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11573 ,  H01L27/11575

Abstract: Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.

公开(公告)号：US20170352669A1

公开(公告)日：2017-12-07

申请号：US15624006

申请日：2017-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer Makala ,  Yanli Zhang ,  Yao-Sheng Lee

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.