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公开(公告)号：US20170276694A1
公开(公告)日：2017-09-28
申请号：US15454231
申请日：2017-03-09
发明人： Jun UEHARA
CPC分类号： G01P3/00 , G01C19/5614 , G01C19/5628 , G01C19/5776 , G01C19/5783 , G01P15/00 , G01P15/125 , G05F3/02 , H03H7/06 , H03M1/122
摘要： A circuit device includes first and second detection circuits which detect physical quantity signals based on detection signals from first and second physical quantity transducers, a multiplexer which selects any one signal among a plurality of signals including the physical quantity signals from the first and second detection circuits, an A/D conversion circuit which performs A/D conversion of the selected signal, and a logic circuit which performs processing of a digital signal from the A/D conversion circuit. The first detection circuit is arranged on a second direction side from a first side of the circuit device. The second detection circuit is arranged on the second direction side from the first side and on a first direction side from the first detection circuit. The A/D conversion circuit is arranged between at least one of the first or second detection circuit and the logic circuit.
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公开(公告)号：US20160269011A1
公开(公告)日：2016-09-15
申请号：US15066054
申请日：2016-03-10
发明人： Jun UEHARA , Takashi AOYAMA
IPC分类号： H03K5/15 , G01P15/09 , G01P15/125 , H03K17/00 , G01C19/5705
CPC分类号： H03K5/15013 , G01C19/5776 , G01P15/0897 , G01P15/09 , G01P15/125 , H03M1/468
摘要： A circuit device includes a multiplexer that selects an input signal from first to n-th input signals in a time division manner and outputs the selected input signal to an output node, an A/D conversion circuit that receives the first to n-th input signals outputted from the multiplexer to the output node in a time division manner and A/D-converts the received first to n-th input signals in a time division manner, and a buffer circuit provided between an i-th input node and the output node of the multiplexer. The buffer circuit buffers the i-th input signal and outputs the buffered signal to the output node of the multiplexer in a first period. The multiplexer selects the i-th input signal and outputs the selected signal to the output node in a second period. End timing of the second period comes after end timing of the first period.
摘要翻译： 电路装置包括多路复用器，其以时分方式从第一至第n输入信号中选择输入信号，并将选择的输入信号输出到输出节点; A / D转换电路，其接收第一至第n输入 以时分方式从多路复用器输出到输出节点的信号，并以时分方式对所接收的第一至第n输入信号进行A / D转换，以及设置在第i个输入节点和输出端之间的缓冲电路 多路复用器的节点。 缓冲电路缓冲第i个输入信号，并在第一周期将缓冲信号输出到多路复用器的输出节点。 多路复用器选择第i个输入信号，并在第二个周期内将选定的信号输出到输出节点。 第二个时期的结束时间是在第一个周期的结束时间之后。
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公开(公告)号：US20200021243A1
公开(公告)日：2020-01-16
申请号：US16505875
申请日：2019-07-09
发明人： Jun UEHARA
摘要： An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, a control terminal that is electrically coupled to the circuit device, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit and sets a potential of the control terminal to an abnormality detection voltage when an abnormal state is detected by the abnormality detection circuit.
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公开(公告)号：US20200018794A1
公开(公告)日：2020-01-16
申请号：US16506027
申请日：2019-07-09
发明人： Jun UEHARA
摘要： An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit, and when an abnormal state is detected by the abnormality detection circuit, the circuit device changes a signal characteristic of the clock signal.
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公开(公告)号：US20230318608A1
公开(公告)日：2023-10-05
申请号：US18192111
申请日：2023-03-29
发明人： Jun UEHARA , Akio TSUTSUMI , Hideki SATO
摘要： A circuit device includes: a first phase comparison circuit including a sampling circuit that samples a feedback signal based on a reference clock signal; a first charge pump circuit configured to output a current corresponding to a sampling voltage; a second phase comparison circuit including a dead zone detection circuit that detects whether a phase difference between the reference clock signal and a feedback clock signal falls within a dead zone, and configured to output a phase difference signal when the phase difference does not fall within the dead zone; a second charge pump circuit; and a clock signal generation circuit configured to generate the clock signal having a frequency controlled based on an output of the first charge pump circuit or the second charge pump circuit. The second charge pump circuit is set disabled or in a low power consumption mode in a dead zone period.
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公开(公告)号：US20200274512A1
公开(公告)日：2020-08-27
申请号：US16794906
申请日：2020-02-19
发明人： Jun UEHARA
摘要： Provided is an oscillator including: a resonator; a first circuit device electrically coupled to the resonator; and a second circuit device. The first circuit device generates a first clock signal by causing the resonator to oscillate, and performs first temperature compensation processing for temperature compensating a frequency of the first clock signal. The second circuit device receives the first clock signal from the first circuit device, generates a second clock signal based on the first clock signal, and performs second temperature compensation processing for temperature compensating a frequency of the second clock signal.
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公开(公告)号：US20180003501A1
公开(公告)日：2018-01-04
申请号：US15541773
申请日：2015-12-25
发明人： Naoki YOSHIDA , Takashi AOYAMA , Jun UEHARA
IPC分类号： G01C19/5705 , G01P15/125 , H01L41/113 , H01L41/053
CPC分类号： G01C19/5705 , G01C19/5621 , G01C19/5628 , G01P1/02 , G01P15/0802 , G01P15/125 , G01P2015/0814 , H01L41/047 , H01L41/053 , H01L41/09 , H01L41/113 , H01L41/1132
摘要： A composite sensor includes a first sensor outputting a first sensor signal, a second sensor outputting a second sensor signal, a circuit board electrically connected to the first and second sensors, and a mount member having one surface on which the first and second sensors and the circuit board are disposed. The first and second sensors have respective input terminals to which respective input signals are inputted, and have respective output terminals from which the first and second sensor signals are outputted. When a virtual straight line passing respective centers of the first and second sensors parallel to an arrangement direction of the sensors is defined, the respective input terminals of the first and second sensors are disposed in one of two regions divided by the virtual line, and the respective output terminals of the first and second sensors are disposed in a remaining one of the two regions.
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