公开(公告)号：US10109580B2

公开(公告)日：2018-10-23

申请号：US15367264

申请日：2016-12-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shunichiro Matsumoto ,  Hitoshi Kondo ,  Katsuya Fukase

IPC: H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.

公开(公告)号：US09699912B2

公开(公告)日：2017-07-04

申请号：US15097473

申请日：2016-04-13

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Toyoaki Sakai ,  Tomoyuki Shimodaira ,  Shunichiro Matsumoto ,  Kentaro Kaneko

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/16 ,  H05K1/11 ,  H05K7/10 ,  H05K7/00 ,  H05K3/00 ,  H05K3/46 ,  H05K1/14 ,  H05K3/34

CPC classification number: H05K3/007 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0191

Abstract: A wiring board includes an insulating layer; and a wiring layer embedded in the insulating layer at one surface side of the insulating layer, one surface of the wiring layer being exposed from one surface of the insulating layer, the wiring layer including a first portion and a second portion whose width is wider than that of the first portion, one surface of the first portion and one surface of the second portion being flush with each other, and the first portion being thinner than the second portion.

公开(公告)号：US09247644B2

公开(公告)日：2016-01-26

申请号：US14329062

申请日：2014-07-11

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Kazuhiro Kobayashi ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Shunichiro Matsumoto ,  Ruofan Tang

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/00 ,  H05K7/10 ,  H05K1/11 ,  H05K3/34 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/2072 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/1184 ,  H05K2203/308

Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.

Abstract translation: 布线基板包括绝缘层，焊盘和阻焊层。 绝缘层具有形成有第一凹部的第一表面。 衬垫嵌入第一凹部。 垫包括第二表面和第三表面。 所述第三表面位于比所述第一表面更低的位置处，以暴露所述第一凹部的内壁表面。 垫在第三表面的中心部分形成有第二凹部。 阻焊层设置在第一表面上。 所述第一表面与所述第一凹部的周边部分的相邻部分的粗糙度小于所述第一表面的相邻部分的周边的第一表面的区域。

公开(公告)号：US20150014027A1

公开(公告)日：2015-01-15

申请号：US14329062

申请日：2014-07-11

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Kazuhiro Kobayashi ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Shunichiro Matsumoto ,  Ruofan Tang

IPC: H05K1/11 ,  H05K1/03

CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/2072 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/1184 ,  H05K2203/308

Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.

Abstract translation: 布线基板包括绝缘层，焊盘和阻焊层。 绝缘层具有形成有第一凹部的第一表面。 衬垫嵌入第一凹部。 垫包括第二表面和第三表面。 所述第三表面位于比所述第一表面更低的位置处，以暴露所述第一凹部的内壁表面。 垫在第三表面的中心部分形成有第二凹部。 阻焊层设置在第一表面上。 所述第一表面与所述第一凹部的周边部分的相邻部分的粗糙度小于所述第一表面的相邻部分的周边的第一表面的区域。