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1.发明公开公开(公告)号：US20240192925A1
公开(公告)日：2024-06-13
申请号：US18325836
申请日：2023-05-30
Applicant: SK hynix Inc.
Inventor： Gi Moon HONG , Dae Han KWON
IPC: G06F7/78 , G11C11/408 , G11C11/4091 , G11C11/4096
CPC classification number: G06F7/78 , G11C11/4085 , G11C11/4091 , G11C11/4096
Abstract: A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.
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公开(公告)号：US20230326496A1
公开(公告)日：2023-10-12
申请号：US18334261
申请日：2023-06-13
Applicant: SK hynix Inc.
Inventor： Kyu Dong HWANG , Bo Ram KIM , Dae Han KWON
IPC: G11C7/10 , H03K19/00 , H03K19/017
CPC classification number: G11C7/1039 , G11C7/1057 , G11C7/1096 , H03K19/01742 , H03K19/0005
Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.
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公开(公告)号：US20220166451A1
公开(公告)日：2022-05-26
申请号：US17412141
申请日：2021-08-25
Inventor： Dongsuk KANG , Jaewoo PARK , Jung-Hoon CHUN , Kyu Dong HWANG , Dae Han KWON
Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.
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公开(公告)号：US20190318772A1
公开(公告)日：2019-10-17
申请号：US16189443
申请日：2018-11-13
Applicant: SK hynix Inc.
Inventor： Bo Ram KIM , Dae Han KWON
Abstract: A sampling circuit may include a first timing determination circuit, a second timing determination circuit, and a sampling data output circuit. The first timing determination circuit may determine a first timing of sampling data in response to a first sampling timing signal. The second timing determination circuit may determine a second timing of the sampling data in response to a second sampling timing signal. The sampling data output circuit may output the sampling data having effective data values of the data between the first timing and the second timing in response to outputs from the first and second timing determination circuits.
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5.发明申请公开(公告)号：US20180375544A1
公开(公告)日：2018-12-27
申请号：US16116724
申请日：2018-08-29
Applicant: SK hynix Inc.
Inventor： Dae Han KWON
Abstract: A receiving device may include a buffer, a summer circuit, a first delay cell, and a second delay cell. The buffer may receive an external signal. The summer circuit may sum an output of the buffer, a first feedback signal, and a second feedback signal. The first delay cell may generate the first feedback signal by delaying an output of the summer circuit. The second delay cell may generate the second feedback signal by delaying the first feedback signal. The delay amounts of the first and second delay cells may be set based on a delay control voltage.
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Patent Agency Ranking
公开(公告)号：US20250117034A1
公开(公告)日：2025-04-10
申请号：US18437743
申请日：2024-02-09
Applicant: SK hynix Inc.
Inventor： Hyungrok DO , Dae Han KWON , Kyu Dong HWANG
Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.
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7.发明公开公开(公告)号：US20240320172A1
公开(公告)日：2024-09-26
申请号：US18351910
申请日：2023-07-13
Applicant: SK hynix Inc.
Inventor： Joon Hong PARK , Dae Han KWON
IPC: G06F13/20
CPC classification number: G06F13/20
Abstract: A semiconductor chip includes a first input/output control circuit configured to generate a first input/output switching signal that controls a first data input/output operation on a first data input/output group according to a first input voltage generated based on an operation voltage, and a second input/output control circuit configured to generate a second input/output switching signal that controls a second data input/output operation on a second data input/output group according to a second input voltage generated based on the operation voltage.
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公开(公告)号：US20240242773A1
公开(公告)日：2024-07-18
申请号：US18320667
申请日：2023-05-19
Applicant: SK hynix Inc.
Inventor： Gi Moon HONG , Dae Han KWON
CPC classification number: G11C29/12015 , G11C7/1066 , G11C7/222 , G11C29/14 , G11C29/18 , G11C2029/1802
Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.
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公开(公告)号：US20220077862A1
公开(公告)日：2022-03-10
申请号：US17159952
申请日：2021-01-27
Applicant: SK hynix Inc.
Inventor： Gi Moon HONG , Dae Han KWON , Kyu Young KIM
Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.
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公开(公告)号：US20210367634A1
公开(公告)日：2021-11-25
申请号：US17083602
申请日：2020-10-29
Applicant: SK hynix Inc.
Inventor： Joo-Hyung CHAE , Dae Han KWON
Abstract: A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.
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