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1.发明申请公开(公告)号：US20140054537A1
公开(公告)日：2014-02-27
申请号：US13791468
申请日：2013-03-08
Applicant: SK HYNIX INC.
Inventor： Seung Yun LEE , Hae Chan PARK , Myoung Sub KIM , Sung Bin HONG , Se Ho LEE , Jung Won SEO
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/16 , H01L45/1683
Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.
Abstract translation: 提供能够防止干扰的电阻式存储装置。 电阻式存储器件包括形成在半导体衬底上的下电极，设置在下电极上的可变电阻器，设置在可变电阻器上的上电极以及被配置为使可变电阻器绝缘的层间绝缘层。 层间绝缘层的至少一部分中可以包括气隙区域。
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公开(公告)号：US20220320427A1
公开(公告)日：2022-10-06
申请号：US17847034
申请日：2022-06-22
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20140325120A1
公开(公告)日：2014-10-30
申请号：US14043524
申请日：2013-10-01
Applicant: SK hynix Inc.
Inventor： Hae Chan PARK , Myoung Sub KIM , Se Ho LEE , Seung Yun LEE
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/15 , G11C2213/73
Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括耦合在字线和位线之间的单元存储单元，其中单元存储单元包括数据存储材料和基于非硅基的类型的双向存取器件，其串联连接 耦合在位线和字线之间的路径设置电路，适于基于路径控制信号，前向写入命令和反向写入命令向位线或字线提供编程脉冲，以及控制 适用于提供基于外部命令信号的写入路径控制信号，正向编程命令和反向编程命令的单元。
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4.发明申请SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR MEMORY APPARATUS AND TEMPERATURE CONTROL METHOD THEREOF 有权包括半导体存储器的半导体系统及其温度控制方法公开(公告)号：US20160086663A1
公开(公告)日：2016-03-24
申请号：US14956823
申请日：2015-12-02
Applicant: SK hynix Inc.
Inventor： Seung Yun LEE , Hae Chan PARK , Myoung Sub KIM , Se Ho LEE
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0033 , G11C13/0038 , G11C2013/008
Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。
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5.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING PHASE-CHANGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开具有相变结构的半导体集成电路装置及其制造方法公开(公告)号：US20150200368A1
公开(公告)日：2015-07-16
申请号：US14255568
申请日：2014-04-17
Applicant: SK hynix Inc.
Inventor： Seung Yun LEE , Kang Sik CHOI
IPC: H01L45/00
CPC classification number: H01L45/1675 , H01L45/06 , H01L45/1625
Abstract: A semiconductor integrated circuit device including a phase-change structure and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a lower electrode, sequentially stacking a plurality of phase-change material layers on the semiconductor substrate, and patterning the stacked plurality of phase-change material layers in a stepwise manner to form a phase-change structure.
Abstract translation: 提供一种包括相变结构的半导体集成电路器件及其制造方法。 该方法包括提供包括下电极的半导体衬底，在半导体衬底上顺序地堆叠多个相变材料层，并且逐步形成层叠的多个相变材料层以形成相变结构。
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Patent Agency Ranking
公开(公告)号：US20150109856A1
公开(公告)日：2015-04-23
申请号：US14158496
申请日：2014-01-17
Applicant: SK hynix Inc.
Inventor： Seung Yun LEE , Hae Chan PARK , Myoung Sub KIM , Se Ho LEE
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0033 , G11C2013/008
Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。
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公开(公告)号：US20140166965A1
公开(公告)日：2014-06-19
申请号：US13846129
申请日：2013-03-18
Applicant: SK HYNIX INC.
Inventor： Jung Won SEO , Hae Chan PARK , Myoung Sub KIM , Sung Bin HONG , Se Ho LEE , Seung Yun LEE
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/124 , H01L45/1608 , H01L45/1666
Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.
Abstract translation: 电阻式存储器件可以包括底部结构，设置在底部结构上的存储单元结构，以及设置成围绕存储单元结构的外侧壁的数据存储材料。
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公开(公告)号：US20210280781A1
公开(公告)日：2021-09-09
申请号：US16984688
申请日：2020-08-04
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20240251687A1
公开(公告)日：2024-07-25
申请号：US18590813
申请日：2024-02-28
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
CPC classification number: H10N70/841 , H10B61/00 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/011 , H10N70/231
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20170162262A1
公开(公告)日：2017-06-08
申请号：US15434458
申请日：2017-02-16
Applicant: SK hynix Inc.
Inventor： Hae Chan PARK , Myoung Sub KIM , Se Ho LEE , Seung Yun LEE
CPC classification number: G11C13/003 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/15 , G11C2213/73
Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
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