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    Signal receiving device, and a semiconductor apparatus and a semiconductor system including the signal receiving device
    3.
    发明授权
    Signal receiving device, and a semiconductor apparatus and a semiconductor system including the signal receiving device 有权

    公开(公告)号：US11539500B2

    公开(公告)日：2022-12-27

    申请号：US17478591

    申请日：2021-09-17

    Applicant: SK hynix Inc.

    Inventor： Soon Sung An ,  Kwan Su Shon ,  Jin Ha Hwang

    IPC: H04L7/00 ,  H04L7/02 ,  H03K19/0175 ,  G11C7/22 ,  G11C7/10

    Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

    Memory device and operating method thereof
    5.
    发明授权
    Memory device and operating method thereof 有权

    公开(公告)号：US11276444B2

    公开(公告)日：2022-03-15

    申请号：US17321601

    申请日：2021-05-17

    Applicant: SK hynix Inc.

    Inventor： Jin Ha Hwang ,  Tai Sik Shin ,  Dong Shin Jo

    IPC: H03K5/24 ,  G11C8/06 ,  G11C8/18

    Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

    Receiver circuit of semiconductor apparatus
    6.
    发明授权
    Receiver circuit of semiconductor apparatus 有权
    半导体装置接收电路

    公开(公告)号：US09520882B2

    公开(公告)日：2016-12-13

    申请号：US14515899

    申请日：2014-10-16

    Applicant: SK hynix Inc.

    Inventor： Jin Ha Hwang

    IPC: H03L7/06 ,  H03K3/356

    CPC classification number: H03L7/06 ,  H03K3/356139 ,  H03K3/356191

    Abstract: A receiver circuit of a semiconductor apparatus may include, a latch comprising differential input terminals and differential output terminals. The receiver circuit may also include a control unit configured to selectively reset first and second intermediate nodes coupled between the differential input terminals and the differential output terminals according to previous data.

    Abstract translation: 半导体装置的接收器电路可以包括：锁存器，其包括差分输入端子和差分输出端子。 接收机电路还可以包括控制单元，其被配置为根据先前的数据选择性地复位耦合在差分输入端子和差分输出端子之间的第一和第二中间节点。

    Voltage generation circuit and input buffer including the voltage generation circuit
    7.
    发明授权
    Voltage generation circuit and input buffer including the voltage generation circuit 有权

    公开(公告)号：US11550347B2

    公开(公告)日：2023-01-10

    申请号：US17840807

    申请日：2022-06-15

    Applicant: SK hynix Inc.

    Inventor： Jin Ha Hwang ,  Soon Sung An

    IPC: G05F1/46 ,  H03F3/45 ,  G05F3/24 ,  H03K17/22

    Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

    Calibration circuit and operating method of the calibration circuit
    9.
    发明授权
    Calibration circuit and operating method of the calibration circuit 有权

    公开(公告)号：US11158356B1

    公开(公告)日：2021-10-26

    申请号：US17097948

    申请日：2020-11-13

    Applicant: SK hynix Inc.

    Inventor： Jin Ha Hwang ,  Kwan Su Shon ,  Keun Seon Ahn ,  Yo Han Jeong ,  Eun Ji Choi

    IPC: G11C5/14 ,  G11C7/10

    Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.

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