公开(公告)号：US11837310B2

公开(公告)日：2023-12-05

申请号：US17569144

申请日：2022-01-05

Applicant: SK hynix Inc.

Inventor： Jaehyeong Hong ,  In Seok Kong ,  Gwan Woo Kim ,  Jae Young Park ,  Kwan Su Shon ,  Soon Sung An ,  Daeho Yang ,  Sung Hwa Ok ,  Junseo Jang ,  Yo Han Jeong ,  Eun Ji Choi

IPC: G11C29/44 ,  G11C29/12 ,  H03K5/15 ,  H03K19/17736 ,  H03K5/156 ,  H03K19/20

CPC classification number: G11C29/4401 ,  G11C29/12015 ,  H03K5/1565 ,  H03K5/15066 ,  H03K19/1774 ,  H03K19/20

Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

公开(公告)号：US12237837B2

公开(公告)日：2025-02-25

申请号：US18085333

申请日：2022-12-20

Applicant: SK hynix Inc.

Inventor： Jaehyeong Hong ,  Junseo Jang ,  In Seok Kong ,  Soon Sung An ,  Dae Ho Yang ,  Kwan Su Shon ,  Yo Han Jeong

IPC: H03K5/1252 ,  G06F1/06 ,  H03K19/21

Abstract: A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.

公开(公告)号：US11962300B2

公开(公告)日：2024-04-16

申请号：US17160089

申请日：2021-01-27

Applicant: SK hynix Inc.

Inventor： Jaehyeong Hong ,  Yo Han Jeong ,  Jin Ha Hwang ,  Junseo Jang

IPC: G11C7/00 ,  G06F1/04 ,  G06F1/26 ,  H03F3/45 ,  H03K3/017 ,  H03K3/037

CPC classification number: H03K3/017 ,  G06F1/04 ,  G06F1/26 ,  H03F3/45264 ,  H03K3/037

Abstract: An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.

公开(公告)号：US11843373B2

公开(公告)日：2023-12-12

申请号：US17514789

申请日：2021-10-29

Applicant: SK hynix Inc.

Inventor： Jin Ha Hwang ,  Soon Sung An ,  Junseo Jang ,  Jaehyeong Hong

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K19/00361

Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.