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公开(公告)号：US11837310B2
公开(公告)日：2023-12-05
申请号：US17569144
申请日：2022-01-05
申请人： SK hynix Inc.
发明人： Jaehyeong Hong , In Seok Kong , Gwan Woo Kim , Jae Young Park , Kwan Su Shon , Soon Sung An , Daeho Yang , Sung Hwa Ok , Junseo Jang , Yo Han Jeong , Eun Ji Choi
CPC分类号： G11C29/4401 , G11C29/12015 , H03K5/1565 , H03K5/15066 , H03K19/1774 , H03K19/20
摘要： The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.
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2.发明授权公开(公告)号：US11962300B2
公开(公告)日：2024-04-16
申请号：US17160089
申请日：2021-01-27
申请人： SK hynix Inc.
发明人： Jaehyeong Hong , Yo Han Jeong , Jin Ha Hwang , Junseo Jang
CPC分类号： H03K3/017 , G06F1/04 , G06F1/26 , H03F3/45264 , H03K3/037
摘要： An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.
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公开(公告)号：US11843373B2
公开(公告)日：2023-12-12
申请号：US17514789
申请日：2021-10-29
申请人： SK hynix Inc.
发明人： Jin Ha Hwang , Soon Sung An , Junseo Jang , Jaehyeong Hong
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/003
CPC分类号： H03K19/018521 , H03K19/00361
摘要： A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.
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