公开(公告)号：US20210391973A1

公开(公告)日：2021-12-16

申请号：US17349775

申请日：2021-06-16

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK ,  Jae Young JANG ,  Byung Cheol KANG ,  Seung Duk CHO

IPC分类号： H04L7/00 ,  H04L7/033

摘要： Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

公开(公告)号：US20140167250A1

公开(公告)日：2014-06-19

申请号：US14185860

申请日：2014-02-20

申请人： SK HYNIX INC.

发明人： Dae Sik PARK

IPC分类号： H01L23/532

CPC分类号： H01L23/53295 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/6656 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/0599

摘要： A semiconductor device and a method of forming the same are disclosed, which forms a low-dielectric-constant oxide film only at a peripheral part of a bit line conductive material, resulting in reduction in parasitic capacitance of the bit line. The semiconductor device includes a bit line formed over a semiconductor substrate, a first spacer formed over sidewalls of the bit line, and a second spacer formed over sidewalls of the first spacer, configured to have a dielectric constant lower than that of the first spacer.

摘要翻译： 公开了半导体器件及其形成方法，其仅在位线导电材料的周边部分形成低介电常数氧化膜，导致位线的寄生电容降低。 半导体器件包括形成在半导体衬底上的位线，在位线的侧壁上形成的第一间隔物，以及形成在第一间隔物的侧壁上的第二间隔物，其被配置为具有低于第一间隔物的介电常数的介电常数。

公开(公告)号：US20240104035A1

公开(公告)日：2024-03-28

申请号：US18534037

申请日：2023-12-08

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Ji Woon YANG ,  Dae Sik PARK

IPC分类号： G06F13/28 ,  G06F13/42

CPC分类号： G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

摘要： An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.

公开(公告)号：US20150235942A1

公开(公告)日：2015-08-20

申请号：US14702605

申请日：2015-05-01

申请人： SK Hynix Inc.

发明人： Dae Sik PARK

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10808 ,  H01L27/10855

摘要： A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.

摘要翻译： 公开了一种半导体器件及其制造方法。 在半导体装置中，存储节点接触插塞的上部尺寸增加，并且在后续处理中形成的存储节点与存储节点接触插头之间的重叠区域增加，使得存储节点的电阻接触 插头增加，设备特性得到改善。 半导体器件包括在半导体衬底上形成的至少一个位线，形成在位线之间并耦合到半导体衬底的上部的第一存储节点接触插塞和形成在第一存储节点上的第二存储节点接触插塞 接触插塞，其中第二存储节点接触插塞的下部的宽度大于其上部的宽度。

公开(公告)号：US20240275573A1

公开(公告)日：2024-08-15

申请号：US18644860

申请日：2024-04-24

申请人： SK hynix Inc.

发明人： Dae Sik PARK ,  Byung Cheol KANG ,  Seung Duk CHO

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/005 ,  H04L7/0079 ,  H04L7/0091 ,  H04L7/033

摘要： A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

公开(公告)号：US20240248819A1

公开(公告)日：2024-07-25

申请号：US18602751

申请日：2024-03-12

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK

IPC分类号： G06F11/20 ,  G06F13/42

CPC分类号： G06F11/2005 ,  G06F13/4221 ,  G06F2201/85 ,  G06F2213/0026

摘要： A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.

公开(公告)号：US20220382705A1

公开(公告)日：2022-12-01

申请号：US17526995

申请日：2021-11-15

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK

IPC分类号： G06F13/42 ,  G06F13/40

摘要： A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

公开(公告)号：US20220382696A1

公开(公告)日：2022-12-01

申请号：US17749133

申请日：2022-05-19

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Ji Woon YANG ,  Dae Sik PARK

IPC分类号： G06F13/28 ,  G06F13/42

摘要： A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US20230353341A1

公开(公告)日：2023-11-02

申请号：US18350220

申请日：2023-07-11

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK ,  Jae Young JANG ,  Byung Cheol KANG ,  Seung Duk CHO

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/005 ,  H04L7/033 ,  H04L7/0091 ,  H04L7/0079

摘要： Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

公开(公告)号：US20220374319A1

公开(公告)日：2022-11-24

申请号：US17751463

申请日：2022-05-23

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK

IPC分类号： G06F11/20 ,  G06F13/42

摘要： A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.