公开(公告)号：US20190057744A1

公开(公告)日：2019-02-21

申请号：US15926011

申请日：2018-03-20

Applicant: SK hynix Inc.

Inventor： Hee Youl LEE ,  Kyoung Cheol KWON ,  Dong Hun LEE ,  Min Kyu JEONG ,  Sung Yong CHUNG

IPC: G11C16/14 ,  G11C16/30

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

公开(公告)号：US20240404874A1

公开(公告)日：2024-12-05

申请号：US18806336

申请日：2024-08-15

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE ,  Jeong Hwan KIM ,  Mi Seong PARK ,  Jung Shik JANG ,  Won Geun CHOI

IPC: H01L21/768

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

公开(公告)号：US20240298446A1

公开(公告)日：2024-09-05

申请号：US18657059

申请日：2024-05-07

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE ,  Mi Seong PARK ,  Jung Shik JANG ,  Jung Dal CHOI ,  In Su PARK

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/34 ,  H10B63/845

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

公开(公告)号：US20230395424A1

公开(公告)日：2023-12-07

申请号：US18450255

申请日：2023-08-15

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE ,  Jeong Hwan KIM ,  Mi Seong PARK ,  Jung Shik JANG ,  Won Geun CHOI

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76838

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

公开(公告)号：US20210020203A1

公开(公告)日：2021-01-21

申请号：US16683027

申请日：2019-11-13

Applicant: SK hynix Inc.

Inventor： Jung Dal CHOI ,  Jung Shik JANG ,  Jin Kook KIM ,  Dong Sun SHEEN ,  Se Young OH ,  Ki Hong LEE ,  Dong Hun LEE ,  Sung Hoon LEE ,  Sung Yong CHUNG

IPC: G11C5/06 ,  H01L27/11582 ,  H01L27/1157

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

公开(公告)号：US20200020403A1

公开(公告)日：2020-01-16

申请号：US16584469

申请日：2019-09-26

Applicant: SK hynix Inc.

Inventor： Hee Youl LEE ,  Kyoung Cheol KWON ,  Dong Hun LEE ,  Min Kyu JEONG ,  Sung Yong CHUNG

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/30

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

公开(公告)号：US20160093381A1

公开(公告)日：2016-03-31

申请号：US14619974

申请日：2015-02-11

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE

IPC: G11C16/10 ,  H01L21/324 ,  H01L27/115

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/20 ,  H01L21/324 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first strong program operation on first memory cells, arranged in a checker board pattern among the memory cells; performing a first annealing process after the first strong program operation; performing a second strong program operation on second memory cells arranged in a reverse checker board pattern among the memory cells, and performing a slight program operation on the first memory cells; and performing a second annealing process after the second strong program operation and the slight program operation.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：形成共享数据存储层的存储单元; 在存储单元中以棋盘图案布置的第一存储单元上执行第一强程序操作; 在第一强编程操作之后执行第一退火处理; 在所述存储单元之间以反向检验板模式布置的第二存储单元执行第二强程序操作，并对所述第一存储单元执行轻微的编程操作; 以及在第二强程序操作和轻微程序操作之后执行第二退火处理。

公开(公告)号：US20230093329A1

公开(公告)日：2023-03-23

申请号：US18071118

申请日：2022-11-29

Applicant: SK hynix Inc.

Inventor： Jung Dal CHOI ,  Jung Shik JANG ,  Jin Kook KIM ,  Dong Sun SHEEN ,  Se Young OH ,  Ki Hong LEE ,  Dong Hun LEE ,  Sung Hoon LEE ,  Sung Yong CHUNG

IPC: G11C5/06 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11568

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

公开(公告)号：US20220149065A1

公开(公告)日：2022-05-12

申请号：US17320813

申请日：2021-05-14

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE ,  Jung Shik JANG

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a peripheral circuit disposed on a substrate; and a gate stack structure overlapping with the peripheral circuit. The gate stack structure includes a plurality of first cell plugs having substantially a cylindrical structure and a plurality of second cell plugs having substantially a hexagonal prism structure.

公开(公告)号：US20220102374A1

公开(公告)日：2022-03-31

申请号：US17216093

申请日：2021-03-29

Applicant: SK hynix Inc.

Inventor： Dong Hun LEE ,  Mi Seong PARK ,  Jung Shik JANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/24

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.